Three-dimensional (3D) NAND component with control circuitry across multiple wafers
Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.
1 . A non-volatile storage component, comprising:
a stack of dies including:
a first die including a first three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the first 3D NAND array; and
a second die vertically stacked on, and bonded with, the first die, wherein the second die is a CMOS control circuitry die lacking a further 3D NAND array, and wherein the second die includes second CMOS control circuitry to access the first 3D NAND array of the first die, wherein the second CMOS control circuitry includes a plurality of wordline exits of a plurality of array wordlines and a plurality of string drivers disposed immediately adjacent to the plurality of wordline exits.
2 . The non-volatile storage component of claim 1 , wherein the first CMOS control circuitry includes page buffers on the first die with the first 3D NAND array.
3 . The non-volatile storage component of claim 1 , wherein a majority of an area of the first die includes page buffer circuitry.
4 . The non-volatile storage component of claim 1 , wherein:
the first 3D NAND array is between the first CMOS control circuitry of the first die and the second CMOS control circuitry of the second die.
5 . The non-volatile storage component of claim 1 , wherein:
the second CMOS control circuitry of the second die is over the first 3D NAND array of the first die; and
the first CMOS control circuitry of the first die is under the first 3D NAND array of the first die.
6 . The non-volatile storage component of claim 1 , wherein:
the second CMOS control circuitry of the second die is under the first 3D NAND array of the first die; and
the first CMOS control circuitry of the first die is over the first 3D NAND array of the first die.
7 . The non-volatile storage component of claim 1 , wherein the first 3D NAND array is located physically between the first CMOS control circuitry of the first die and the second CMOS control circuitry of the second die.
8 . The non-volatile storage component of claim 1 , wherein the plurality of string drivers are placed on top of the 3D NAND array in the stack of dies, and configured to drive the plurality of array wordlines of the 3D NAND array.
9 . A three-dimensional (3D) NAND memory component comprising:
a first die comprising a first three-dimensional (3D) NAND array of memory cells and first complementary metal oxide semiconductor (CMOS) control circuitry;
a second die vertically stacked on, and bonded with, the first die, the second die including second CMOS control circuitry,
wherein array control circuitry to access the first 3D NAND array is disposed on both the first die and the second die, and a location of the NAND memory cells is limited to the first die;
wherein the second CMOS control circuitry includes a plurality of wordline exits of a plurality of array wordlines and a plurality of string drivers disposed immediately adjacent to the plurality of wordline exits.
10 . The 3D NAND memory component of claim 9 , wherein:
the first CMOS control circuitry includes page buffers on the first die with the first 3D NAND array.
11 . The 3D NAND memory component of claim 9 , wherein a majority of an area of the first die includes page buffer circuitry.
12 . The 3D NAND memory component of claim 9 , wherein:
the first 3D NAND array is between the first CMOS control circuitry of the first die and the second CMOS control circuitry of the second die.
13 . The 3D NAND memory component of claim 9 , further comprising:
a third die vertically stacked on, and bonded with, the second die, wherein the third die includes a second 3D NAND array and third CMOS control circuitry to access the second 3D NAND array;
wherein the second CMOS control circuitry of the second die is configured to access both the first 3D NAND array of the first die and the second 3D NAND array of the third die.
14 . The 3D NAND memory component of claim 13 , wherein the first CMOS control circuitry includes first page buffer circuitry for the first 3D NAND array, and the third CMOS control circuitry includes second page buffer circuitry for the second 3D NAND array, and wherein the plurality of string drivers of the second CMOS control circuitry are configured to drive both the first 3D NAND array and the second 3D NAND array.
15 . The 3D NAND memory component of claim 13 , wherein the second die is physically disposed between the first die and the third die.