STRUCTURE AND METHOD OF INCREASING SUBTRACTIVE BITLINE AIR GAP HEIGHT
Systems, apparatuses, and methods may provide for technology for forming extended air gaps for bitline contacts. For example, such technology patterns and etches a dielectric layer and a bitline layer to create bitline contacts in a memory die. An air gap dielectric layer is deposited to form an air gap between adjacent bitline contacts, and wherein the air gap has a height dimension that extends past a height dimension of the bitline contacts.
1 . A memory die comprising:
a memory array; and
a bitline structure coupled to the memory array, the bitline structure comprising:
a plurality of bitline contacts;
a dielectric layer position above the plurality of bitline contacts;
an air gap dielectric layer positioned above the plurality of bitline contacts; and
an air gap positioned between adjacent bitline contacts of the plurality of bitline contacts, wherein the air gap has an air gap height dimension that extends past a bitline contact height dimension of the plurality of bitline contacts.
2 . The memory die of claim 1 , wherein the air gap extends into the air gap dielectric layer.
3 . The memory die of claim 1 , wherein the air gap height dimension extends past a dielectric layer height dimension of the dielectric layer.
4 . The memory die of claim 1 , wherein the plurality of bitline contacts comprise one or more of tungsten, aluminum, copper, and molybdenum.
5 . The memory die of claim 1 , wherein the plurality of bitline contacts are constructed through a subtractive bitline formation process.
6 . The memory die of claim 1 , wherein the memory die comprises 3D-NAND memory.
7 . A solid state drive (SSD) comprising:
a memory controller; and
a memory device coupled to the memory controller, the memory device comprising:
a memory array; and
a bitline structure coupled to the memory array, the bitline structure comprising:
a plurality of bitline contacts;
a dielectric layer position above the plurality of bitline contacts;
an air gap dielectric layer positioned above the plurality of bitline contacts; and
an air gap positioned between adjacent bitline contacts of the plurality of bitline contacts, wherein the air gap has an air gap height dimension that extends past a bitline contact height dimension of the plurality of bitline contacts.
8 . The solid state drive (SSD) of claim 7 , wherein the air gap extends into the air gap dielectric layer.
9 . The solid state drive (SSD) of claim 7 , wherein the air gap height dimension extends past a dielectric layer height dimension of the dielectric layer.
10 . The solid state drive (SSD) of claim 7 , wherein the plurality of bitline contacts comprise one or more of tungsten, aluminum, copper, and molybdenum.
11 . The solid state drive (SSD) of claim 7 , wherein the plurality of bitline contacts are constructed through a subtractive bitline formation process.
12 . The solid state drive (SSD) of claim 7 , wherein the memory device comprises 3D-NAND memory.
13 . A method comprising:
patterning and etching a dielectric layer and a bitline layer to create bitline contacts in a memory die; and
depositing an air gap dielectric layer to form an air gap between adjacent bitline contacts, and wherein the air gap has an air gap height dimension that extends past a bitline contact height dimension of the bitline contacts.
14 . The method of claim 13 , wherein the air gap extends into the air gap dielectric layer.
15 . The method of claim 13 , wherein the air gap height dimension extends past a dielectric layer height dimension of the dielectric layer.
16 . The method of claim 13 , further comprising:
depositing the bitline layer above a substrate of the memory die.
17 . The method of claim 16 , further comprising:
capping the bitline layer with the dielectric layer.
18 . The method of claim 13 , wherein the bitline layer comprises one or more of tungsten, aluminum, copper, and molybdenum.
19 . The method of claim 13 , wherein the bitline contacts are constructed through a subtractive bitline formation process via the etching.
20 . The method of claim 13 , wherein the memory die comprises 3D-NAND memory.