Simultaneous programming of multiple sub-blocks in NAND memory structures

1. A memory chip controller comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:

boost strings of a plurality of NAND sub-blocks to a pass voltage, and bypass a boost of an initial NAND sub-block in the plurality of NAND sub-blocks;

deboost a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks; and

simultaneously program the first subset while a second subset of the boosted strings remain at the pass voltage.

2. The memory chip controller of claim 1 , wherein to boost the strings of the plurality of NAND sub-blocks, the logic is to apply the pass voltage to selected and unselected wordlines that are connected to the plurality of NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the plurality of NAND sub-blocks.

3. The memory chip controller of claim 1 , wherein to deboost the first subset of the boosted strings, the logic is to:

apply first data associated with a first sub-block to a bitline;

connect, via a first drain-side select gate, the first sub-block to the bitline;

apply second data associated with a second sub-block to the bitline; and

connect, via a second drain-side select gate, the second sub-block to the bitline.

4. The memory chip controller of claim 3 , wherein at least a portion of one or more of the first data or the second data is to be applied at an intermediate voltage level that is between an inhibit voltage level and a program voltage level.

5. The memory chip controller of claim 3 , wherein the first sub-block and the second sub-block are to be connected to the bitline momentarily.

6. The memory chip controller of claim 3 , wherein the first sub-block is to be connected to the bitline momentarily and the second sub-block is to be connected to the bitline until the first subset is programmed.

7. The memory chip controller of claim 1 , wherein to simultaneously program the first subset, the logic is to:

apply a program pulse to selected wordlines that are connected to the plurality of NAND sub-blocks; and

apply a single set of verify pulses to the selected wordlines.

8. The memory chip controller of claim 1 , further including a plurality of latches, wherein the logic is to store one or more of sub-block state data, page state data or the data associated with the plurality of NAND sub-blocks to the plurality of latches.

9. A computing system comprising:

a system on chip (SoC); and

a solid state drive coupled to the SoC, the solid state drive including a plurality of NAND sub-blocks and a memory chip controller, wherein the memory chip controller includes logic to:

boost strings of the plurality of NAND sub-blocks to a pass voltage, and bypass a boost of an initial NAND sub-block in the plurality of NAND sub-blocks,

deboost a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and

simultaneously program the first subset while a second subset of the boosted strings remain at the pass voltage.

10. The computing system of claim 9 , wherein to boost the strings of the plurality of NAND sub-blocks, the logic is to apply the pass voltage to selected and unselected wordlines that are connected to the plurality of NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the plurality of NAND sub-blocks.

11. The computing system of claim 9 , wherein to deboost the first subset of the boosted strings, the logic is to:

apply first data associated with a first sub-block to a bitline,

connect, via a first drain-side select gate, the first sub-block to the bitline,

apply second data associated with a second sub-block to the bitline, and

connect, via a second drain-side select gate, the second sub-block to the bitline.

12. The computing system of claim 11 , wherein at least a portion of one or more of the first data or the second data is to be applied at an intermediate voltage level that is between an inhibit voltage level and a program voltage level.

13. The computing system of claim 11 , wherein the first sub-block and the second sub-block are to be connected to the bitline momentarily.

14. The computing system of claim 11 , wherein the first sub-block is to be connected to the bitline momentarily and the second sub-block is to be connected to the bitline until the first subset is programmed.

15. The computing system of claim 9 , wherein to simultaneously program the first subset, the logic is to:

apply a program pulse to selected wordlines that are connected to the plurality of NAND sub-blocks, and

apply a single set of verify pulses to the selected wordlines.

16. The computing system of claim 9 , wherein the memory chip controller further includes a plurality of latches, and wherein the logic is to store one or more of sub-block state data, page state data or the data associated with the plurality of NAND sub-blocks to a plurality of latches.

17. A method comprising:

boosting strings of a plurality of NAND sub-blocks to a pass voltage, and bypass a boost of an initial NAND sub-block in the plurality of NAND sub-blocks;

deboosting a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks; and

simultaneously programming the first subset while a second subset of the boosted strings remain at the pass volage.

18. The method of claim 17 , wherein boosting the strings of the plurality of NAND sub-blocks includes applying the pass voltage to selected and unselected wordlines that are connected to the plurality of NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the plurality of NAND sub-blocks.