Modulation of source voltage in NAND-flash array read
Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
1. A NAND storage device comprising:
a storage array including a plurality of strings of NAND memory cells coupled with a source line; and
logic to perform a read operation, the logic to:
ramp up wordline voltages of the plurality of strings;
apply a first source voltage to the source line with a magnitude greater than a second source voltage applied to the source line during sensing;
turn off unselected select gates; and
after turning off the unselected select gates, apply the second source voltage to the source line.
2. The NAND storage device of claim 1 , wherein:
the logic to perform the read operation is to:
apply the first source voltage to the source line during the ramp up of the wordline voltages and in response to one or more signals indicating the storage array is idle.
3. The NAND storage device of claim 1 , wherein:
the logic to perform the read operation is to:
apply the second source voltage to the source line in response to one or more signals indicating the storage array is not idle.
4. The NAND storage device of claim 3 , wherein:
the logic to perform the read operation is to:
in response to detection that the wordline voltages reached a target voltage VPASS, ramp down a selected wordline voltage from a first target voltage VPASS to a second target voltage; and
wherein application of the second source voltage to the source line is after the ramp down of the selected wordline voltage to the second target voltage.
5. The NAND storage device of claim 4 , wherein:
the application of the second source voltage to the source line is after a predetermined delay after the ramp down of the selected wordline voltage to the second target voltage.
6. The NAND storage device of claim 1 , wherein the logic to turn off the unselected select gates is to:
turn off unselected SGSs (select-gate-source), SGDs (select-gate-drain) on unselected SGSs, and SGDs on unselected sub-blocks on a selected SGS in response to detection that the wordline voltages reached a first target voltage VPASS.
7. The NAND storage device of claim 1 , wherein:
the logic to perform the read operation is to:
apply the first source voltage to the source line after sensing in response to one or more signals indicating the storage array is idle.
8. The NAND storage device of claim 7 , wherein:
the logic to perform the read operation is to:
apply the second source voltage to the source line in response to the one or more signals indicating the storage array is not idle.
9. The NAND storage device of claim 1 , wherein the logic to turn off the unselected select gates is to:
turn off unselected SGSs (select-gate-source), SGDs (select-gate-drain) on the unselected SGSs, and SGDs on unselected sub-blocks on a selected SGS after a predetermined time after the ramp up of the wordline voltages.
10. The NAND storage device of claim 1 , wherein:
the first source voltage has the magnitude that is lower than a second magnitude of: the second source voltage plus a first target voltage VPASS to ramp up the wordline voltages to, minus a maximum threshold voltage of the NAND memory cells with a 0V source reference.
11. A system comprising:
a processor; and
a NAND storage device coupled with the processor, the NAND storage device including:
a storage array including a plurality of strings of NAND memory cells coupled with a source line; and
logic to perform a read operation, the logic to:
ramp up wordline voltages of the plurality of strings;
apply a first source voltage to the source line with a magnitude greater than a second source voltage applied to the source line during sensing;
turn off unselected select gates; and
after turning off the unselected select gates, apply the second source voltage to the source line.
12. The system of claim 11 , wherein:
the logic to perform the read operation is to:
apply the first source voltage to the source line during the ramp up of the wordline voltages and in response to one or more signals indicating the storage array is idle.
13. The system of claim 11 , wherein:
the logic to perform the read operation is to:
apply the second source voltage to the source line in response to one or more signals indicating the storage array is not idle.
14. The system of claim 13 , wherein:
the logic to perform the read operation is to:
in response to detection that the wordline voltages reached a target voltage VPASS, ramp down a selected wordline voltage from a first target voltage VPASS to a second target voltage; and
wherein application of the second source voltage to the source line is after the ramp down of the selected wordline voltage to the second target voltage.
15. The system of claim 14 , wherein:
the application of the second source voltage to the source line is after a predetermined delay after the ramp down of the selected wordline voltage to the second target voltage.
16. The system of claim 11 , wherein the logic to turn off the unselected select gates is to:
turn off unselected SGSs (select-gate-source), SGDs (select-gate-drain) on the unselected SGSs, and SGDs on unselected sub-blocks on a selected SGS in response to detection that the wordline voltages reached a first target voltage VPASS.
17. The system of claim 11 , further comprising one or more of:
a display coupled with the processor, a network interface coupled with the processor, and a battery to power the system.
18. A solid state drive (SSD) comprising:
input/output (I/O) interface circuitry to couple with a host, the I/O interface circuitry to receive a read request; and
one or more dies including:
a NAND storage array, the NAND storage array including a plurality of strings of NAND memory cells coupled with a source line; and
logic to perform a read operation in response to the read request, the logic to:
ramp up wordline voltages of the plurality of strings;
apply a first source voltage to the source line with a magnitude greater than a second source voltage applied to the source line during sensing;
turn off unselected select gates; and
after turning off the unselected select gates, apply the second source voltage to the source line.
19. The SSD of claim 18 , wherein:
the logic to perform the read operation is to:
apply the first source voltage to the source line during the ramp up of the wordline voltages and in response to one or more signals indicating the NAND storage array is idle.
20. The SSD of claim 18 , wherein:
the logic to perform the read operation is to:
apply the second source voltage to the source line in response to one or more signals indicating the NAND storage array is not idle.