IP Library Granted Patent US 6,974,715
Granted Patent B2
US 6,974,715 · App. 10/669,996 · Granted Dec 13, 2005

Method for manufacturing CMOS image sensor using spacer etching barrier film

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Quick Facts
Patent No.
US 6,974,715
App. No.
10/669,996
Granted
Dec 13, 2005
Kind
B2
Abstract

A method for fabricating a CMOS image sensor including a low voltage buried photodiode and a transfer transistor, includes the steps of: forming a field oxide for defining active area and field area on certain area of an epitaxial layer formed on a substrate, and forming a gate of transfer transistor on the epitaxial layer of the active area; forming the low voltage buried photodiode doping region in alignment with one side of the gate of transfer transistor and field oxide; forming a spacer insulation layer by stacking layers of oxide and nitride over the whole structure; forming a spacer block mask to open areas excluding doping region for the low voltage buried photodiode; and removing the spacer block mask, and forming a floating diffusion region on other side of the transfer transistor. Alternatively, the sacrificial nitride may be allowed to remain on the surface of the photodiode to improve optical properties for short wavelength lights.

Claims (13)

1. A method for fabricating a complimentary metal-oxide-silicon (CMOS) image sensor including a low voltage buried photodiode and a transfer transistor, the method comprising:

a) forming a field oxide for defining an active area and a field area on a certain area of an epitaxial layer formed on a substrate, and forming a gate of a transfer transistor on the epitaxial layer of the active area;

b) forming a low voltage buried photodiode doping region in alignment with one side of the gate of the transfer transistor;

c) forming a spacer insulation layer by stacking layers of oxide and nitride on the entire resulting structure of part (b);

d) forming a spacer block mask on the spacer insulation layer to open area opposite the transfer transistor from the low voltage buried photodiode doping region while leaving the photodiode doping region covered by the spacer insulation layer and spacer block mask; and

e) removing the spacer insulation layer not covered by the spacer block mask to form a spacer on a sidewall of the transistor, and removing the spacer block mask.

2. The method for fabricating CMOS image sensor as recited in claim 1 , wherein the oxide layer of the spacer insulation layer has a thickness ranging from about 200 Å to about 2000 Å, and the nitride layer of the spacer insulation layer has a thickness ranging from about 200 Å to about 1000 Å.

3. The method for fabricating CMOS image sensor as recited in claim 1 , wherein part b) further comprises: sequentially performing n-type ion implantation and p-type ion implantation using a first mask with an opening disposed over the low voltage buried photodiode doping region.

4. The method for fabricating CMOS image sensor as recited in claim 3 , wherein the spacer block mask of part d) is formed using the first mask of part b) and a negative photoresist.

5. A CMOS image sensor made in accordance with the method of claim 1 .

6. The method for fabricating CMOS image sensor as recited in claim 1 , further comprising:

forming a second mask over the portion of the space insulation layer remaining on the photodiode doping region and leaving the area opposite the transfer transistor open; and

forming a floating diffusion region on the open area opposite the transfer transistor from the photodiode doping region while the second mask and the remaining portion of the space insulation layer is in place over the photodiode doping region.

Assignments (10)
NUNC PRO TUNC ASSIGNMENT Recorded May 9, 2017
From: CARL ZEISS SMT GMBH
To: CARL ZEISS AG
Reel/Frame 042307/0072 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2017
From: INTELLECTUAL VENTURES FUND 99 LLC
To: TARSIUM B.V.
Reel/Frame 042172/0466 →
NUNC PRO TUNC ASSIGNMENT Recorded Apr 28, 2017
From: TARSIUM B.V.
To: ASML NETHERLANDS B.V.; CARL ZEISS SMT GMBH
Reel/Frame 042172/0767 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2014
From: INTELLECTUAL VENTURES II LLC
To: INTELLECTUAL VENTURES FUND 99 LLC
Reel/Frame 033039/0775 →
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2004
From: LEE, JU-IL
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014954/0610 →