Semiconductor device and chip-stack semiconductor device
View Patent ↗A semiconductor device has multiple power-supply through electrodes, grounding through electrodes, and signal-routing through electrodes made through a semiconductor chip. The power-supply through electrodes, the grounding through electrodes, and the signal-routing through electrodes differ mutually in cross-sectional area. Hence, a semiconductor device and a chip-stack semiconductor device are provided which are capable of preventing the electrodes' resistance from developing excessive voltage drop, heat, delay, and loss, and also from varying from one electrode to the other.
1. A semiconductor device, comprising:
a semiconductor chip;
multiple through electrodes formed in the semiconductor chip linking a front surface to a back surface thereof,
wherein said multiple through electrodes comprise a first through electrode and a second through electrode, and
wherein said first through electrode and said second through electrode have mutually differing cross-sectional areas in a common horizontal plane transverse to a through-hole direction; and
wherein at least one type of the through electrodes is contact through electrodes electrically connected to the semiconductor chip, and wherein at least one type of the through electrodes is non-contact through electrodes not electrically connected to the semiconductor chip.
2. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas are increased according to a magnitude of an electric current via the through electrodes.
3. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas are increased according to a magnitude of an electric current via the through electrodes.
4. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas are increased according to a magnitude of an electric current via the through electrodes.
5. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas of those through electrodes which are connected to a ground terminal or a power supply terminal of the semiconductor chip are greater than the cross-sectional areas of those through electrodes which are connected to a signal terminal.
6. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas of those through electrodes which are connected to a ground terminal or a power supply terminal of the semiconductor chip are greater than the cross-sectional areas of those through electrodes which are connected to a signal terminal.
7. The semiconductor device as set forth in claim 1 , wherein the cross-sectional areas of those through electrodes which are connected to a ground terminal or a power supply terminal of the semiconductor chip are greater than the cross-sectional areas of those through electrodes which are connected to a signal terminal.
8. A semiconductor device, comprising:
multiple through electrodes in a semiconductor chip linking a front surface to a back surface thereof,
wherein the through electrodes have mutually differing cross-sectional areas, and
wherein at least one type of the through electrodes is non-contact through electrodes not electrically connected to the semiconductor chip.
9. The semiconductor device as set forth in claim 8 , wherein the cross-sectional areas are increased according to a magnitude of an electric current via the through electrodes.
10. The semiconductor device as set forth in claim 8 , wherein the cross-sectional areas of those through electrodes which are connected to a ground terminal or a power supply terminal of the semiconductor chip are greater than the cross-sectional areas of those through electrodes which are connected to a signal terminal.
11. A chip-stack semiconductor device, comprising multiple stacked semiconductor chips,
each of the semiconductor chips including multiple through electrodes therein linking a front surface to a back surface thereof,
wherein said multiple through electrodes comprise a first through electrode and a second through electrode, and
wherein:
the first and second through electrodes have mutually differing cross-sectional areas in a common horizontal plane transverse to a through-hole direction; and
at least one type of the through electrodes is contact through electrodes electrically connected to that semiconductor chip; and
wherein the cross-sectional areas are increased according to an interconnect line length through the multiple stacked semiconductor chips.
12. The chip-stack semiconductor device as set forth in claim 11 , wherein the cross-sectional areas of those through electrodes which connect n+1 or more adjacent semiconductor chips are greater than the cross-sectional areas of those through electrodes which connect n adjacent semiconductor chips, where n is an integer more than or equal to 2.
13. The chip-stack semiconductor device as set forth in claim 11 , wherein the cross-sectional areas are increased in proportion to an interconnect line length through the multiple stacked semiconductor chips.
14. A chip-stack semiconductor device, comprising
multiple stacked semiconductor chips, each of the semiconductor chips including multiple through electrodes therein linking a front surface to a back surface thereof,
wherein:
the through electrodes have mutually differing cross-sectional areas; and
at least one type of the through electrodes is non-contact through electrodes not electrically connected to that semiconductor chip.
15. The chip-stack semiconductor device as set forth in claim 14 , wherein the cross-sectional areas of those through electrodes which connect n+1 or more adjacent semiconductor chips are greater than the cross-sectional areas of those through electrodes which connect n adjacent semiconductor chips, where n is an integer more than or equal to 2.
16. The chip-stack semiconductor device as set forth in claim 14 , wherein the cross-sectional areas are increased according to an interconnect line length through the multiple stacked semiconductor chips.
17. The chip-stack semiconductor device as set forth in claim 16 , wherein the cross-sectional areas are increased in proportion to an interconnect line length through the multiple stacked semiconductor chips.
18. A chip-stack semiconductor device, comprising
multiple stacked semiconductor chips, each of the semiconductor chips including multiple through electrodes therein linking a front surface to a back surface thereof,
wherein:
the through electrodes have mutually differing cross-sectional areas;
at least one type of the through electrodes is contact through electrodes electrically connected to that semiconductor chip; and
at least one type of the through electrodes is non-contact through electrodes not electrically connected to that semiconductor chip.
19. The chip-stack semiconductor device as set forth in claim 18 , wherein the cross-sectional areas of those through electrodes which connect n+1 or more adjacent semiconductor chips are greater than the cross-sectional areas of those through electrodes which connect n adjacent semiconductor chips, where n is an integer more than or equal to 2.
20. The chip-stack semiconductor device as set forth in claim 18 , wherein the cross-sectional areas are increased according to an interconnect line length through the multiple stacked semiconductor chips.
21. The chip-stack semiconductor device as set forth in claim 20 , wherein the cross-sectional areas are increased in proportion to an interconnect line length through the multiple stacked semiconductor chips.
22. A chip-stack semiconductor device, comprising:
multiple stacked semiconductor chips, each of the semiconductor chips including multiple through electrodes therein linking a front surface to a back surface thereof,
wherein the through electrodes have mutually differing cross-sectional areas, and
wherein the cross-sectional areas are increased according to an interconnect line length through the multiple stacked semiconductor chips.
23. The chip-stack semiconductor device as set forth in claim 22 , wherein the cross-sectional areas are increased in proportion to an interconnect line length through the multiple stacked semiconductor chips.