Yield maximization in the manufacture of integrated circuits
View Patent ↗A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.
1. In a semiconductor manufacturing environment where logic functions are implemented by coupling together of a plurality of different types of standard cells, each type of standard cell implementing a particular logic function, a method for improving yield of integrated circuits through the semiconductor manufacturing environment, the method comprising the steps of:
designing a plurality of different variants for the standard cells in a library, each of the plurality of different standard cell variants addressing a different manufacturing problem;
selecting standard cells in one standard cell variant to be used in a particular manufacturing environment to optimize the yield of integrated circuits fabricated using the selected standard cells; and
coupling together the selected standard cells to implement the logic functions wherein each of the variants is assigned a manufacturability rating, the step of selecting a standard cell variant being influenced by the assigned manufacturability rating.
2. In a semiconductor manufacturing environment where logic functions are implemented by coupling together of a plurality of different types of standard cells, each type of standard cell implementing a particular logic function, a method for improving yield of integrated circuits through the semiconductor manufacturing environment, the method comprising the steps of:
designing a plurality of different variants for the standard cells in a library, each of the plurality of different standard cell variants addressing a different manufacturing problem, wherein the variants are designed to at least address the manufacturing problems of poor contact formation, contact alignment, metal line spacing and metal line direction changes;
selecting standard cells in one standard cell variant to be used in a particular manufacturing environment to optimize the yield of integrated circuits fabricated using the selected standard cells; and
coupling together the selected standard cells to implement the logic functions.
3. In a semiconductor manufacturing environment where logic functions are implemented by coupling together of a plurality of different types of standard cells, each type of standard cell implementing a particular logic function, a method for improving yield of integrated circuits through the semiconductor manufacturing environment, the method comprising the steps of:
designing a plurality of different variants for the standard cells in a library, each of the plurality of different standard cell variants addressing a different manufacturing problem;
selecting standard cells in one standard cell variant to be used in a particular manufacturing environment to optimize the yield of integrated circuits fabricated using the selected standard cells; and
coupling together the selected standard cells to implement the logic functions.
4. In an integrated circuit design environment wherein multiple standard components are used to form an integrated circuit design, a method for allowing an integrated circuit designer to optimize the integrated circuit design, the method comprising the steps of:
designing a plurality of variants of the multiple standard components wherein the variants are designed to at least address the manufacturing problems of poor contact formation, contact alignment, metal line spacing and metal line direction changes;
rating each variant on at least one variable; and
selecting the variant whose rating most closely matches designer's criteria for use in the integrated circuit design.
5. The method of claim 4 wherein the standard components comprise standard logic cells.
6. The method of claim 4 wherein the standard components comprise input/output cells.
7. The method of claim 4 wherein the standard components comprise memory core cells or entire memory blocks including core cells.
8. The method of claim 4 wherein the standard components perform at least an analog function, the analog function including one of at least phase locked loops and analog-to-digital converters.
9. The method of claim 4 wherein each of the standard components and its variants are characterized to indicate the manufacturing yield of the particular variant.
10. The method of claim 4 wherein the variants of standard components comprise variants of standard logic cells.
11. The method of claim 10 wherein the variants of standard logic cells have each been assigned a rating which indicates its manufacturability in at least a manufacturing environment.
12. The method of claim 11 wherein the variants of standard logic cells have a plurality of different manufacturability ratings, a different rating being assigned for each different potential manufacturing environment.
13. A system for improving the manufacturability of an integrated circuit, the system comprising:
a library comprised of a plurality of variant designs for standard components of the integrated circuit, each of the plurality of variant designs compensating for at least a known manufacturing problem; and
a synthesis tool coupled to the library, the synthesis tool formulating and presenting to a user a proposed integrated circuit design, the proposed integrated circuit design incorporating a variant design that corrects for a known manufacturing problem encountered in a particular manufacturing environment selected by the user.
14. The system of claim 13 wherein the library is further comprised of a plurality of variant designs of standard logic cells.
15. The system of claim 13 wherein the library is further comprised of a plurality of variant designs of memory core cells.
16. The system of claim 13 wherein the library is further comprised of a plurality of variant designs of input/output cells.
17. A system for improving the manufacturability of an integrated circuit, the system comprising:
a library comprised of a plurality of variant designs for standard components of the integrated circuit, each of the plurality of variant designs compensating for at least a known manufacturing problem; and
a synthesis tool coupled to the library, the synthesis tool formulating and presenting to a user a proposed integrated circuit design, the proposed integrated circuit design incorporating a variant design that corrects for a known manufacturing problem encountered in a particular manufacturing environment selected by the user wherein the library is further comprised of a plurality of variant designs of standard logic cells and wherein the plurality of variant designs of standard logic cells are rated on a manufacturability index, a different rating being assigned to each variant design for each manufacturing environment in which it is used.
18. A system for improving the manufacturability of an integrated circuit, the system comprising:
a library comprised of a plurality of variant designs for standard components of the integrated circuit, each of the plurality of variant designs compensating for at least a known manufacturing problem; and
a synthesis tool coupled to the library, the synthesis tool formulating and presenting to a user a proposed integrated circuit design, the proposed integrated circuit design incorporating a variant design that corrects for a known manufacturing problem encountered in a particular manufacturing environment selected by the user wherein the plurality of variant designs also include compensation for a design related integrated circuit yield limiter, the integrated circuit yield limiters including at least leakage current through transistors.