Patent Assignment
Reel/Frame 017619/0154
Merger/Change of Name
Recorded: 2006-05-15
Received: 2006-05-15
Pages: 10
Assignor
ARTISAN COMPONENTS, INC.
Executed: 2004-12-23
Assignee
ARM PHYSICAL IP, INC.
141 CASPIAN COURT, SUNNYVALE, CA, 94089-1013, UNITED STATES
Covered Properties
(27)
Dynamically Adaptable Memory
Application:
10/833,388 →
Feed-Forward Circuit for Reducing Delay Through an Input Buffer
Application:
10/759,339 →
Dual Port Memory Core Cell Architecture with Matched Bit Line Capacitances
Application:
10/727,760 →
Yield Maximization in the Manufacture of Integrated Circuits
Application:
10/671,029 →
Method for Identification of Faulty or Weak Functional Logic Elements Under Simulated Extreme Operating Conditions
Application:
10/665,862 →
Voltage Tolerant Circuit for Protecting an Input Buffer
Application:
10/630,949 →
Method and Apparatus for Reducing Write Power Consumption in Random Access Memories
Application:
10/460,626 →
Leakage Current Reduction in Standard Cells
Application:
10/448,636 →
Negatively Charged Wordline for Reduced Subthreshold Current
Application:
10/364,719 →
System and Method for Low Area Self-Timing in Memory Devices
Application:
10/364,720 →
System and Method for Row Decode in a Multiport Memory
Application:
10/364,198 →
Method and Apparatus for a Dense Metal Programmable Rom
Application:
10/350,497 →
Method and Apparatus for Reducing Process-Induced Charge Buildup
Application:
10/191,931 →
Memory Column Redundancy Circuitry and Method for Implementing the Same
Application:
10/179,773 →
Method and Apparatus for Gain Compensation and Control in Low Voltage Differential Signaling Applications
Application:
10/172,206 →
Method and Apparatus for Voltage Clamping in Feedback Amplifiers Using Resistors
Application:
10/170,526 →
Load Independent Single Ended Sense Amplifier
Application:
10/113,759 →
System and Method for Identification of Faulty or Weak Memory Cells Under Simulated Extreme Operating Conditions
Application:
10/077,837 →
System and Method for Assured Built in Self Repair of Memories
Application:
10/074,517 →
Zero Power Fuse Sensing Circuit for Redundancy Applications in Memories
Application:
10/074,559 →
Methods for Reducing Bitline Voltage Offsets in Memory Devices
Application:
10/026,246 →
Memories Having Reduced Bitline Voltage Offsets
Application:
10/026,245 →
Low Voltage Differential Signaling Circuit with Mid-Point Bias
Application:
09/991,107 →
Power/Ground Metallization Routing in a Semiconductor Device
Application:
09/929,320 →
Method and Apparatus for a Dense Metal Programmable Rom
Application:
09/896,444 →
Method and Apparatus for a Dense Metal Programmable Rom
Application:
09/896,055 →
System and Method for Setup and Hold Characterization in Integrated Circuit Cells
Application:
09/841,797 →