Dual port memory core cell architecture with matched bit line capacitances
View Patent ↗A Static Random Access Memory (SRAM) dual port memory with an improved core cell design having internally matched capacitances and decreased bit line capacitance is disclosed. The core cell is fabricated on a substrate divided into three approximately equal columns of different substrate materials. In a preferred embodiment, the memory cell is fabricated on a central p-type column that in turn is sandwiched between two n-type columns. The three-column substrate architecture permits reduced bit line height, with an accompanying reduction in bit line capacitance, which increases the speed at which the core cell can operate. The architecture also permits separating the core cell's bitline and complement bitline, reducing capacitive coupling between these lines and increasing the core cell's operating speed. The architecture further permits better matching of internal node capacitances.
1. A core cell, the core cell fabricated on a substrate, comprising:
the substrate being defined of three columns of substrate material, the three columns of substrate material comprising a first p-type column, a first n-type column and a second p-type column, the n-type column being positioned between the first and second p-type columns; and
a pair of bitlines coupled to the core cell, such that the bitlines are separated by at least one of a voltage supply line and a ground voltage line, the bitlines not running in parallel immediately adjacent to one another.
2. The core cell of claim 1 , wherein the bitline and complementary bitline are separated by one of at least a ground line and a voltage supply line.
3. In a random access memory comprised of at least a plurality of core cells, a core cell, comprising:
first p-type substrate;
first n-type substrate;
second p-type substrate, the first and second p-type substrates being positioned on opposite sides of the first n-type substrate; and
a pair of bitlines coupled to the core cell, wherein the bitlines are separated by at least one of a voltage supply line and a ground voltage line, the bitlines not running in parallel immediately adjacent to one another.
4. The core cell of claim 3 , wherein each substrate has a generally rectangular shape, the rectangles having substantially the same area.
5. The core cell of claim 3 , wherein at least two PMOS transistors are fabricated on the first n-type substrate.
6. The core cell of claim 5 , wherein at least 4 NMOS transistors are fabricated on the first and second p-type substrate.
7. The core cell of claim 6 , wherein the two PMOS transistors and two NMOS transistors are coupled together to form two inverters, the two inverters being coupled together to form the core cell's storage element.