Differential output circuit for improving bandwidth
View Patent ↗A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.
1. An integrated circuit comprising:
a logic circuit developing first and second input signals complementary to each other, wherein said logic circuit includes:
a first pull-up N-channel MISFET used for pull-up of said first input signal, and
a second pull-up N-channel MISFET used for pull-up of said second input signal; and
a differential output circuit including:
a first input receiving said first input signal;
a second input receiving said second input signal;
first and second outputs;
a resistor element connected between said first and second outputs;
a first N-channel MISFET having a source connected to said first input, a gate receiving a power supply potential, and a drain connected to said first output;
a second N-channel MISFET having a source connected to said second input, a gate receiving said power supply potential, and a drain connected to said second output;
a first P-channel MISFET having a source receiving said power supply potential, a gate connected to said second input, and a drain connected to said first output; and
a second P-channel MISFET having a source receiving said power supply potential, a gate connected to said first input, and a drain connected to said second output.
2. The integrated circuit according to claim 1 , further comprising an inductive element, wherein said resistive element and said inductive element are connected in series between said first and second outputs.
3. An integrated circuit comprising:
a logic circuit developing first and second input signals complementary to each other, wherein said logic circuit includes:
a first pull-up N-channel MISFET used for pull-up of said first input signal, and
a second pull-up N-channel MISFET used for pull-up of said second input signal; and
a differential output circuit including:
a first input receiving said first input signal;
a second input receiving said second input signal;
first and second outputs;
an inductive element connected between said first and second outputs;
a first N-channel MISFET having a source connected to said first input, a gate receiving a power supply potential, and a drain connected to said first output;
a second N-channel MISFET having a source connected to said second input, a gate receiving said power supply potential, and a drain connected to said second output;
a first P-channel MISFET having a source receiving said power supply potential, a gate connected to said second input, and a drain connected to said first output; and
a second P-channel MISFET having a source receiving said power supply potential, a gate connected to said first input, and a drain connected to said second output.