Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
A circuit, apparatus and method for maximizing system margins by adjusting a duty-cycle of a clock signal in a receive circuit to whatever duty-cycle is optimal for the particular incoming serial data, rather than the typical 50% duty-cycle, is provided in embodiments of the present invention. A receive circuit, including duty-cycle-correction logic, is included in a double-data rate communication apparatus having a transmit circuit transmitting serial data having duty-cycle distortion. A receive circuit includes a first and second sampler to obtain data and edge values of an incoming serial data responsive to a data and edge clock, respectively. A duty-cycle-correction logic generates a duty-cycle-correction signal to a duty-cycle clock integrator that adjusts the edge clock signals while maintaining quadrature to the data clocks. In an embodiment of the present invention, a duty-cycle-correction logic includes an evaluator circuit to generate an up or down signal responsive to the data and/or edge values. In a further embodiment of the present invention, an evaluator circuit is coupled to a counter and a DAC to generate a duty-cycle-correction signal to the duty-cycle clock integrator. A digital filter or coding scheme is also used to reduce the likelihood of misinterpreting malevolent incoming serial data for duty-cycle distortion in an embodiment of the present invention.
1. A circuit capable to receive an input signal having a duty-cycle, comprising:
a first sampler capable to obtain a first edge value from the input signal responsive to an edge clock signal;
a second sampler capable to obtain a first data value from the input signal responsive to a data clock signal; and,
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock signal to the duty-cycle of the input signal duty-cycle responsive to the first edge value and first data value.
2. The circuit of claim 1 , wherein the data clock signal has an approximate 50% duty-cycle and is in quadrature with an adjusted edge clock signal.
3. The circuit of claim 1 , further comprising:
a third sampler, coupled to the duty-cycle-correction logic, capable to obtain a second data value; and,
wherein the duty-cycle-correction logic is capable to generate the duty-cycle-correction signal responsive to the first data value, first edge value and second data value.
4. The circuit of claim 3 , wherein the duty-cycle-correction logic comprises:
an evaluator circuit capable to generate at least one of an up signal and a down signal, responsive to the first data value, first edge value and second data value; and,
a duty-cycle clock integrator, coupled to the evaluator circuit, capable to generate the duty-cycle-correction signal responsive to the at least one of the up and down signal.
5. The circuit of claim 4 , further comprising:
a first phase comparator, coupled to the first sampler, capable to generate the data clock signal; and,
a second phase comparator, coupled to the first duty-cycle clock integrator and the second sampler, capable to generate the edge clock signal responsive to the duty-cycle-correction signal.
6. The circuit of claim 1 , wherein the input signal is a double-data rate signal and the circuit is included in a double-data rate system.
7. The circuit of claim 1 , wherein the circuit is included in a memory module coupled to a double-data rate bus.
8. A circuit capable to receive an input signal having a duty-cycle, comprising:
a first sampler capable to obtain a first edge value from the input signal responsive to an edge clock signal;
a second sampler capable to obtain a second edge value from the input signal responsive to the edge clock signal; and
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock signal to the duty-cycle of the input signal duty-cycle responsive to the first and second edge values.
9. The circuit of claim 8 , wherein a data clock signal has an approximate 50% duty-cycle and is in quadrature with an adjusted edge clock signal.
10. The circuit of claim 8 , wherein the duty-cycle-correction logic comprises:
an evaluator circuit capable to generate at least one of an up signal and a down signal, responsive to the first and second edge values; and,
a duty-cycle clock integrator, coupled to the evaluator circuit, capable to generate the duty-cycle-correction signal responsive to the at least one of the up and down signal.
11. The circuit of claim 10 , further comprising:
a first phase comparator, coupled to the duty-cycle clock integrator and the first and second samplers, capable to generate the edge clock signal responsive to the duty-cycle-correction signal.
12. The circuit of claim 8 , wherein the input signal is a double-data rate signal and the circuit is included in a double-data rate system.
13. The circuit of claim 8 , wherein the circuit is included in a memory module coupled to a double-data rate bus.
14. A circuit capable to receive an input signal having a duty-cycle, comprising:
a first sampler capable to obtain a first edge value from the input signal responsive to an edge clock signal;
a second sampler capable to obtain a second edge value from the input signal responsive to the edge clock signal;
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock to the duty-cycle of the input signal responsive to the first and second edge values;
wherein the duty-cycle-correction logic includes,
an evaluator circuit, coupled to the first and second samplers, capable to generate an adjust signal, responsive to the first and second edge values;
a counter, coupled to the evaluator circuit, capable to output a count value responsive to the adjust signal;
a digital-to-analog-converter, coupled to the counter, capable to generate an analog offset signal responsive to the count signal; and,
a duty-cycle clock integrator, coupled to the digital-to-analog-converter, capable to generate the duty-cycle-correction signal responsive to the analog offset signal.
15. The circuit of claim 14 , wherein a data clock signal has an approximate 50% duty-cycle and is in quadrature with an adjusted edge clock signal.
16. The circuit of claim 14 , further comprising;
a digital filter coupled to first and second samplers and the evaluator circuit.
17. The circuit of claim 16 , wherein the input signal is a coded input signal having an approximate same number of even and odd data transitions.
18. The circuit of claim 14 , further comprising:
a first phase comparator, coupled to the duty-cycle clock integrator and the first and second samplers, capable to generate the edge clock signal responsive to the duty-cycle-correction signal.
19. The circuit of claim 14 , wherein the input signal is a double-data rate signal and the circuit is included in a double-data rate system.
20. The circuit of claim 14 , wherein the circuit is included in a memory module coupled to a double-data rate bus.
21. An apparatus, comprising:
a transmit circuit capable to transmit a serial signal having a duty-cycle;
a receive circuit, coupled to the transmit circuit, including
a first sampler capable to obtain a first edge value from the serial signal responsive to an edge clock signal;
a second sampler capable to obtain a first data value from the serial signal responsive to a data clock signal; and,
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock signal to the duty-cycle of the serial signal duty-cycle responsive to the first edge value and first data value.
22. An apparatus, comprising:
a transmit circuit capable to transmit a serial signal having a duty-cycle; and,
a receive circuit, coupled to the transmit circuit, including
a first sampler capable to obtain a first edge value from the serial signal responsive to an edge clock signal;
a second sampler capable to obtain a second edge value from the serial signal responsive to the edge clock signal; and,
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock to the duty-cycle of the serial signal duty-cycle responsive to the first and second edge values.
23. An apparatus, comprising:
a transmit circuit capable to transmit a serial signal having a duty-cycle; and,
a receive circuit, coupled to the transmit circuit, including,
a first sampler capable to obtain a first edge value from the serial signal responsive to an edge clock signal;
a second sampler capable to obtain a second edge value from the serial signal responsive to the edge clock signal;
a duty-cycle-correction logic, coupled to the first and the second samplers, capable to generate a duty-cycle-correction signal that adjusts the edge clock to the duty-cycle of the serial signal responsive to the first and second edge values;
wherein the duty-cycle-correction logic includes,
an evaluator circuit, coupled to the first and second samplers, capable to generate an adjust signal, responsive to the first and second edge values;
a counter, coupled to the evaluator circuit, capable to output a count value responsive to the adjust signal; and,
a digital-to-analog-converter, coupled to the counter, capable to generate the duty-cycle-correction signal responsive to the count signal.
24. A method, comprising the steps of:
receiving an input signal having a first duty-cycle;
sampling the input signal to obtain a plurality of edge values from the input signal responsive to an edge clock signal having a second duty-cycle; and,
adjusting the second duty-cycle of the edge clock signals to the first duty-cycle of the input signal responsive to the plurality of edge values.
25. The method of claim 24 , further comprising the steps of:
sampling the input signal to obtain a plurality of data values from the input signal responsive to a data clock signal.
26. The method of claim 25 , wherein the adjusting step includes adjusting the data clock signal to have an approximate 50duty-cycle and be in quadrature with an adjusted edge clock signal.
27. A circuit capable to receive an input signal having a duty-cycle, comprising:
a sampler capable to obtain a plurality of edge values from the input signal responsive to an edge clock signal having a duty-cycle; and,
means, coupled to the sampler, for adjusting the edge clock signal duty-cycle to the input signal duty-cycle.