Random access memory cell having reduced current leakage and having a pass transistor control gate formed in a trench
View Patent ↗A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell ( 300 ) includes a storage capacitor ( 304 ) and a pass transistor ( 302 ). The pass transistor ( 302 ) includes a source region ( 322 ), drain region ( 320 ) and channel region ( 324 ). A top gate ( 318 ) is disposed over the channel region ( 324 ) and a bottom gate ( 310 ) is disposed below the channel region ( 324 ). The top gate ( 318 ) and bottom gate ( 310 ) are commonly driven to provide greater control of the pass transistor ( 302 ) operation, including an off state with reduced source-to-drain leakage. The DRAM array ( 400 ) includes memory cells ( 414 ) having pass transistors ( 500 ) with double-gate structures. Memory cells ( 414 ) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer ( 600 ). The DRAM array ( 400 ) further includes a strapping area that is void of memory cells. Conductive contact between the top word line, bottom word line, and word line strap layer ( 600 ) of each row is made within the strapping area by way of strapping vias ( 604 ) and top-to-bottom word line vias ( 602 ).
1. A random access memory cell, comprising:
a data storage node; and
a pass transistor coupled to the data storage node to provide charge transfer to and from the data storage node and including
a source region,
a drain region,
a channel region disposed between the source region and the drain region, the channel region including a first channel side and a second channel side opposite to the first channel side,
a first channel side control gate, and
a second channel side control gate wherein
the first channel side control gate is formed in a trench.
2. The random access memory cell of claim 1 , further including:
a substrate insulator layer providing electrical isolation between the first channel side control gate and a substrate.
3. The random access memory cell of claim 2 , wherein:
the trench is at least partially defined by the substrate insulator layer.
4. The random access memory cell of claim 1 , further including:
a first channel side gate insulating layer disposed between the first channel side control gate and the first channel side.
5. The random access memory cell of claim 4 , wherein:
the first channel side gate insulating layer include thermally grown silicon dioxide.
6. The random access memory cell of claim 1 , wherein:
the first channel side control gate includes doped polysilicon.
7. The random access memory cell of claim 1 , wherein:
a second channel side gate insulating layer disposed between the second channel side control gate and the second channel side.
8. The random access memory cell of claim 7 , wherein:
the second channel side gate insulating layer include thermally grown silicon dioxide.
9. The random access memory cell of claim 1 , wherein:
the data storage node includes polysilicon.
10. The random access memory cell of claim 1 , wherein:
the first channel side control gate and the second channel control side gate are electrically connected to a word line; and
the word line is electrically connected to a word line driver.
11. The random access memory cell of claim 1 , wherein:
the data storage node is a first terminal of a storage capacitor.
12. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a capacitor dielectric layer including nitride.
13. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a capacitor dielectric layer including Si 3 N 4 .
14. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a capacitor dielectric layer including Ta 2 O 3 .
15. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a capacitor dielectric layer including SrTiO 3 .
16. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a capacitor dielectric layer including BaSrTiO 3 .
17. The random access memory cell of claim 11 , wherein:
the storage capacitor includes a second terminal shared with at least another storage capacitor of another random access memory cell.
18. The random access memory cell of claim 11 , wherein;
the storage capacitor is a trench capacitor.
19. The random access memory cell of claim 11 , wherein:
the storage capacitor has a capacitor-over-bit line structure.
20. The random access memory cell of claim 11 , wherein: the storage capacitor has a capacitor-under-bit line structure.
21. The random access memory cell of claim 1 , wherein:
the pass transistor is coupled to provide charge transfer between the storage node and a bit line; and
the bit line includes metal from the group consisting of Ti, Al, and Cu.