IP Library Granted Patent US 7,020,769
Granted Patent B2
US 7,020,769 · App. 10/675,092 · Granted Mar 28, 2006

Method and system for processing a loop of instructions

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Quick Facts
Patent No.
US 7,020,769
App. No.
10/675,092
Granted
Mar 28, 2006
Kind
B2
Abstract

An information handling system processes a loop of instructions. In response to detecting processing of a particular instruction during a pass through the loop, the system initiates a fetch of an initial instruction that is programmed at a start of the loop, and stores an identification of a different instruction that is programmed between the initial instruction and the particular instruction. According to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, the system initiates an additional fetch of the initial instruction.

Claims (41)

1. A method performed by an information handling system in processing a loop of instructions, comprising:

in response to detecting processing of a particular instruction during a pass through the loop, initiating a fetch of an initial instruction that is programmed at a start of the loop, and storing an identification of a different instruction that is programmed between the initial instruction and the particular instruction; and

according to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, initiating an additional fetch of the initial instruction.

2. The method of claim 1 , wherein initiating the fetch comprises:

in response to detecting processing of the particular instruction during the pass through the loop, initiating the fetch before processing a final instruction during the additional pass, wherein the final instruction is programmed at an end of the loop.

3. The method of claim 1 , wherein initiating the additional fetch comprises:

in response to detecting processing of the different instruction during the additional pass through the loop, initiating the additional fetch before processing a final instruction during the additional pass, wherein the final instruction is programmed at an end of the loop.

4. The method of claim 1 , wherein the particular instruction is an instruction that includes an end-of-loop alert associated with the loop.

5. The method of claim 1 , wherein the particular instruction is an instruction at which an end-of-loop mark is located in association with the loop.

6. The method of claim 1 , wherein the loop is a first loop, and wherein the information handling system processes multiple loops of instructions including the first loop and a second loop, and wherein initiating the fetch comprises:

in response to detecting processing of the particular instruction during the pass through the loop, initiating the fetch if the first loop is an innermost nested loop that contains the particular instruction and is scheduled to be repeated in the additional pass before processing an instruction outside the first loop.

7. The method of claim 6 , wherein initiating the additional fetch comprises:

in response to detecting processing of the different instruction during the additional pass through the loop, initiating the additional fetch if the first loop is an innermost nested loop that contains the different instruction and is scheduled to be repeated in yet another pass before processing an instruction outside the first loop.

8. The method of claim 7 , wherein the particular instruction is a first particular instruction, the initial instruction is a first initial instruction, the different instruction is a first different instruction, and the stored identification is a first stored identification, and comprising:

in response to detecting processing of a second particular instruction during a pass through the second loop, initiating a fetch of a second initial instruction that is programmed at a start of the second loop, and storing a second identification of a second different instruction that is programmed between the second initial instruction and the second particular instruction; and

according to the second stored identification, in response to detecting processing of the second different instruction during an additional pass through the second loop, initiating an additional fetch of the second initial instruction.

9. The method of claim 8 , wherein initiating the fetch of the second initial instruction comprises:

in response to detecting processing of the second particular instruction during the pass through the second loop, initiating the fetch if the second loop is an innermost nested loop that contains the second particular instruction and is scheduled to be repeated in the additional pass before processing an instruction outside the second loop.

10. The method of claim 9 , wherein initiating the additional fetch of the second initial instruction comprises:

in response to detecting processing of the second different instruction during the additional pass through the second loop, initiating the additional fetch if the second loop is an innermost nested loop that contains the second different instruction and is scheduled to be repeated in yet another pass before processing an instruction outside the second loop.

11. A system for processing a loop of instructions, comprising:

circuitry for:

in response to detecting processing of a particular instruction during a pass through the loop, initiating a fetch of an initial instruction that is programmed at a start of the loop, and storing an identification of a different instruction that is programmed between the initial instruction and the particular instruction; and

according to the stored identification, in response to detecting processing of the different instruction during an additional pass through the loop, initiating an additional fetch of the initial instruction.

12. The system of claim 11 , wherein the circuitry is for:

in response to detecting processing of the particular instruction during the pass through the loop, initiating the fetch before processing a final instruction during the additional pass, wherein the final instruction is programmed at an end of the loop.

13. The system of claim 11 , wherein the circuitry is for:

in response to detecting processing of the different instruction during the additional pass through the loop, initiating the additional fetch before processing a final instruction during the additional pass, wherein the final instruction is programmed at an end of the loop.

14. The system of claim 11 , wherein the particular instruction is an instruction that includes an end-of-loop alert associated with the loop.

15. The system of claim 11 , wherein the particular instruction is an instruction at which an end-of-loop mark is located in association with the loop.

16. The system of claim 11 , wherein the loop is a first loop, and wherein the system processes multiple loops of instructions including the first loop and a second loop, and wherein the circuitry is for:

in response to detecting processing of the particular instruction during the pass through the loop, initiating the fetch if the first loop is an innermost nested loop that contains the particular instruction and is scheduled to be repeated in the additional pass before processing an instruction outside the first loop.

17. The system of claim 16 , wherein the circuitry is for:

in response to detecting processing of the different instruction during the additional pass through the loop, initiating the additional fetch if the first loop is an innermost nested loop that contains the different instruction and is scheduled to be repeated in yet another pass before processing an instruction outside the first loop.

18. The system of claim 17 , wherein the particular instruction is a first particular instruction, the initial instruction is a first initial instruction, the different instruction is a first different instruction, and the stored identification is a first stored identification, and wherein the circuitry is for:

in response to detecting processing of a second particular instruction during a pass through the second loop, initiating a fetch of a second initial instruction that is programmed at a start of the second loop, and storing a second identification of a second different instruction that is programmed between the second initial instruction and the second particular instruction; and

according to the second stored identification, in response to detecting processing of the second different instruction during an additional pass through the second loop, initiating an additional fetch of the second initial instruction.

19. The system of claim 18 , wherein the circuitry is for:

in response to detecting processing of the second particular instruction during the pass through the second loop, initiating the fetch of the second initial instruction if the second loop is an innermost nested loop that contains the second particular instruction and is scheduled to be repeated in the additional pass before processing an instruction outside the second loop.

20. The system of claim 19 , wherein the circuitry is for:

in response to detecting processing of the second different instruction during the additional pass through the second loop, initiating the additional fetch of the second initial instruction if the second loop is an innermost nested loop that contains the second different instruction and is scheduled to be repeated in yet another pass before processing an instruction outside the second loop.

Assignments (19)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
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To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
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To: LSI CORPORATION; AGERE SYSTEMS LLC
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
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PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
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From: FREESCALE SEMICONDUCTOR, INC.
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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