Patent Assignment
Reel/Frame 040652/0180
Change of Name
Recorded: 2016-11-08
Pages: 44
Assignor
FREESCALE SEMICONDUCTOR INC.
Executed: 2016-11-07
Assignee
NXP USA, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TEXAS, 78735
Covered Properties
(1464)
Apparatus and Method for Managing Data-Flow Dependencies Arising from Out-of-Order Execution, by an Execution Unit, of an Instruction Series Input from an Instruction Source
Patent:
5,872,949 →
Application:
08/748,459 →
Apparatus and Method for Implementing a Content Addressable Memory Circuit with Two Stage Matching
Patent:
5,893,137 →
Application:
08/753,752 →
Serial Interface 3WITH Register Selection Which Uses Clock Counting, Chip Select Pulsing, and No Address Bits
Patent:
5,941,974 →
Application:
08/757,606 →
Class a Amplifier with a Digitally Programmable Miller Compensation Network
Patent:
5,877,654 →
Application:
08/758,658 →
Temperature Sensor
Patent:
5,829,879 →
Application:
08/772,710 →
Electronic Device for Controlling a Reactance Value for a Reactive Element
Patent:
5,777,522 →
Application:
08/775,991 →
Beta Dependent Temperature Sensor for an Integrated Circuit
Patent:
6,160,305 →
Application:
08/777,924 →
Process for Polishing a Semiconductor Device Substrate
Patent:
5,916,011 →
Application:
08/780,113 →
Apparatus for Dicing a Semiconductor Device Substrate and a Process Therefor
Patent:
5,904,547 →
Application:
08/780,119 →
Method for Measuring a Characteristic of a Semiconductor Wafer Using Cylindrical Control
Patent:
5,982,166 →
Application:
08/790,260 →
Low Power Schmitt Trigger
Patent:
5,886,556 →
Application:
08/791,441 →
Method for Reducing Particles on a Substrate Using Chuck Cleaning
Patent:
5,966,635 →
Application:
08/791,970 →
Process for Producing and Inspecting a Lithographic Reticle and Fabricating Semiconductor Devices Using Same
Patent:
5,849,440 →
Application:
08/792,670 →
Input Stage for an Analog-to-Digital Converter and Method of Operation Thereof
Patent:
5,760,728 →
Application:
08/794,622 →
Quiescent Current Monitor Curcuit for Wafer Level Integrated Circuit Testing
Patent:
5,912,562 →
Application:
08/795,027 →
Method and Apparatus for Synchronizing Multiple Clocks
Patent:
5,742,799 →
Application:
08/801,648 →
Process for Forming a Semiconductor Device Having a Ferroelectric Capacitor
Patent:
5,750,419 →
Application:
08/803,789 →
One Dimensional Lithographic Proximity Correction Using Drc Shape Functions
Patent:
5,900,340 →
Application:
08/805,863 →
Cascaded Integrator-Comb Interpolation Filter
Patent:
5,880,687 →
Application:
08/806,271 →
Two Dimensional Lithographic Proximity Correction Using Drc Shape Functions
Patent:
5,920,487 →
Application:
08/810,561 →
Circuit and Process for Sensing Data
Patent:
5,929,659 →
Application:
08/815,526 →
Automatic Transition Charge Pump for Nonvolatile Memories
Patent:
5,801,987 →
Application:
08/818,273 →
Process for Forming a Semiconductor Device
Patent:
5,958,508 →
Application:
08/828,635 →
Process for Forming a Semiconductor Device
Patent:
6,068,668 →
Application:
08/829,297 →
Semiconductor Device Having a Metal Containing Layer Overlying a Gate Dielectric
Patent:
6,084,279 →
Application:
08/831,287 →
Integrated Circuit Having Standby Control for Memory and Method Thereof
Patent:
5,901,103 →
Application:
08/835,363 →
Pulse Width Modulator (Pwm) System with Low Cost Dead Time Distortion Correction
Patent:
5,764,024 →
Application:
08/835,370 →
Plug Protection Process for Use in the Manufacture of Embedded Dynamic Random Access Memory (Dram) Cells
Patent:
5,773,314 →
Application:
08/845,457 →
Static Pulsed Cross-Coupled Level Shifter and Method Therefor
Patent:
5,896,045 →
Application:
08/851,261 →
Method and Apparatus for Positioning a Restrictor Shield of a Pump in Response to an Electric Signal
Patent:
6,000,415 →
Application:
08/855,827 →
Process for Depositing a Layer of Material Over a Substrate
Patent:
6,174,425 →
Application:
08/856,459 →
Method and Apparatus for Verifying and Characterizing Data Retention Time in a Dram Using Built-in Test Circuitry
Patent:
6,272,588 →
Application:
08/865,510 →
Data Processing System Having a Synchronizing Link Stack and Method Therefof
Patent:
6,157,999 →
Application:
08/868,467 →
Method of Making and Accesing Split Gate Memory Device
Patent:
5,824,584 →
Application:
08/876,326 →
Split-Gate Memory Device and Method for Accessing the Same
Patent:
5,969,383 →
Application:
08/876,576 →
Method for Manufacturing a High Dielectric Constant Gate Oxide for Use in Semiconductor Integrated Circuits
Patent:
6,063,698 →
Application:
08/885,433 →
Semiconductor Package Bond Post Configuration
Patent:
5,898,213 →
Application:
08/888,392 →
Method and Apparatus for Moving Data in a Parallel Processor Using Source and Destination Vector Registers
Patent:
6,088,782 →
Application:
08/891,228 →
Process for Forming a Semiconductor Device
Patent:
5,821,168 →
Application:
08/895,017 →
Dual Bandwidth Phase Locked Loop Frequency Lock Detection System and Method
Patent:
6,215,834 →
Application:
08/905,336 →
Method for Forming High Dielectric Constant Metal Oxides
Patent:
6,020,024 →
Application:
08/905,755 →
Low Selectivity Chemical Mechanical Polishing (Cmp) Process for Use on Integrated Circuit Metal Interconnects
Patent:
6,045,435 →
Application:
08/905,757 →
Method for Forming an Mos Transistor Having a Metallic Gate Electrode That Is Formed After the Formation of Self-Aligned Source and Drain Regions
Patent:
5,960,270 →
Application:
08/907,990 →
Methods of Designing a Reticle and Forming a Semiconductor Device Therewith
Patent:
5,827,625 →
Application:
08/912,601 →
Method and Apparatus for Processing a Semiconductor Wafer on a Robotic Track Having Access to in Situ Wafer Backside Particle Detection
Patent:
5,963,315 →
Application:
08/912,726 →
Process for Forming a Semiconductor Device
Patent:
5,935,871 →
Application:
08/916,297 →
Method and Apparatus for Managing Failure of a System Clock in a Data Processing System
Patent:
5,903,748 →
Application:
08/916,733 →
Digital Output Buffer for Multiple Voltage System
Patent:
6,040,729 →
Application:
08/917,306 →
Method of Chemical Mechanical Planarization Using a Water Rinse to Prevent Particle Contamination
Patent:
6,071,816 →
Application:
08/921,131 →
Method and Apparatus for Providing Operand Feed Forward Support in a Data Processing System
Patent:
6,145,097 →
Application:
08/924,117 →
Memory Controller and Method for Generating Commands to a Memory
Patent:
6,226,724 →
Application:
08/929,128 →
Method and Apparatus for Testing a Circuit Module Concurrently with a Non-Volatile Memory Operation in a Multi-Module Data Processing System
Patent:
6,076,177 →
Application:
08/935,572 →
Data Processing System with Memory Patching and Method Thereof
Patent:
6,073,252 →
Application:
08/937,451 →
Segmented Bus Architecture (Sba) for Electrostatic Discharge (Esd) Protection
Patent:
6,046,897 →
Application:
08/939,284 →
Circuit for Electrostatic Discharge (Esd) Protection
Patent:
5,903,419 →
Application:
08/939,637 →
Circuit for Electrostatic Discharge (Esd) Protection
Patent:
5,917,336 →
Application:
08/939,764 →
Semiconductor Device Having Multiple Overlapping Rows of Bond Pads with Conductive Interconnects and Method of Pad Placement
Patent:
5,962,926 →
Application:
08/940,605 →
Unbuffered Latch Resistant to Back-Writing and Method of Operation Therefor
Patent:
5,905,393 →
Application:
08/944,777 →
Method for Forming a Conductive Structure Having a Composite or Amorphous Barrier Layer
Patent:
6,136,682 →
Application:
08/954,149 →
Lithographic Proximity Correction Through Subset Feature Modification
Patent:
5,958,635 →
Application:
08/954,160 →
Chemical Mechanical Polishing (Cmp) Slurry for Polishing Copper Interconnects Which Use Tantalum-Based Barrier Layers
Patent:
6,001,730 →
Application:
08/954,191 →
System and Method for Recovering a Microprocessor from a Locked Bus State
Patent:
5,961,622 →
Application:
08/956,966 →
Method and Circuit for Controlling a Precharge Cycle of a Memory Device
Patent:
5,828,612 →
Application:
08/958,646 →
Process for Forming a Semiconductor Device
Patent:
5,972,804 →
Application:
08/963,436 →
Method of Chemical Mechanical Planarization Using Copper Coordinating Ligands
Patent:
6,096,652 →
Application:
08/963,438 →
Simd Computation of Rank Based Filters for M X N Grids
Patent:
6,058,405 →
Application:
08/965,686 →
Data Processor with a Privileged State Firewall and Method Therefore
Patent:
6,003,133 →
Application:
08/972,069 →
Method for Forming a Tensile Plasma Enhanced Nitride Capping Layer Over a Gate Electrode
Patent:
6,284,633 →
Application:
08/976,469 →
Method and Output Buffer with Programmable Bias to Accommodate Multiple Supply Voltages
Patent:
5,917,358 →
Application:
08/987,361 →
Computer Instruction Which Generates Multiple Results of Different Data Types to Improve Software Emulation
Patent:
6,039,765 →
Application:
08/990,780 →
Method and Apparatus for Implementing Floating Point Projection Intructions
Patent:
6,049,865 →
Application:
08/993,514 →
Process for Forming a Semiconductor Device Having an Interconnect or Conductive Film Electrically Insulated from a Conductive Member or Region
Patent:
6,184,073 →
Application:
08/997,714 →
Multiple Bist Controllers for Testing Multiple Embedded Memory Arrays
Patent:
5,995,731 →
Application:
08/998,564 →
Semiconductor Device Including a Substrate Having Clustered Interconnects
Patent:
5,898,217 →
Application:
09/002,610 →
Method for Making a Semiconductor Device
Patent:
6,171,959 →
Application:
09/009,396 →
Method and Apparatus for High Voltage Generation
Patent:
6,054,825 →
Application:
09/010,044 →
Voltage Regulator with Automatic Accelerated Aging Circuit
Patent:
6,091,287 →
Application:
09/012,414 →
Fuse Circuit and Method Therefor Which Minimizes Fuse Grow Back Effect
Patent:
6,021,078 →
Application:
09/014,389 →
Method and Apparatus for Providing a Clocking Signal
Patent:
5,966,054 →
Application:
09/015,846 →
Method for Forming Interconnect Bumps on a Semiconductor Die
Patent:
6,107,180 →
Application:
09/015,956 →
Method for Forming an Integrated Circuit
Patent:
6,133,093 →
Application:
09/015,957 →
Comparison Circuit Utilizing a Diffrential Amplifier
Patent:
5,973,955 →
Application:
09/016,940 →
Leadframe Having Continuously Reducing Width and Semiconductor Device Including Such a Leadframe
Patent:
5,932,924 →
Application:
09/016,988 →
Flip Chip Bump Structure and Method of Making
Patent:
5,977,632 →
Application:
09/017,562 →
Data Processing System External Pin Connectivity to Complex Functions
Patent:
6,145,104 →
Application:
09/022,396 →
Method for Forming a Semiconductor Device
Patent:
6,344,413 →
Application:
09/022,756 →
Method and Apparatus for Equallization in an Asymmetric Digital Aubscriber Line Communications System
Patent:
6,047,025 →
Application:
09/023,061 →
Tantalum Oxide Anti-Reflective Coating (Arc) Integrated with a Metallic Transistor Gate Electrode and Method of Formation
Patent:
6,004,850 →
Application:
09/028,101 →
Multi-Chip Semiconductor Device and Method for Making the Device by Using Multiple Flip Chip Interfaces
Patent:
6,150,724 →
Application:
09/032,860 →
Semiconductor Device Having Plated Contacts and Method Thereof
Patent:
5,990,547 →
Application:
09/033,048 →
Semiconductor Device Inhibiting Parasitic Effects During Electrostatic Discharge and Method of Forming Same
Patent:
6,075,271 →
Application:
09/033,752 →
Method and Apparatus for Performing Voltage Sampling
Patent:
6,057,713 →
Application:
09/038,751 →
Fuseless Memory Repair System and Method of Operation
Patent:
6,011,734 →
Application:
09/038,752 →
Integrated Circuit Having Output Timing Control Circuit and Method Thereof
Patent:
6,011,749 →
Application:
09/049,221 →
Design and Methodology for Manufacturing Data Processing Systems Having Multiple Processors
Patent:
6,067,633 →
Application:
09/052,248 →
Voltage Recovery Circuit and Method Therefor
Patent:
6,008,677 →
Application:
09/053,896 →
Method for Performing Branch Prediction and Resolution of Two or More Branch Instructions Within Two or More Branch Prediction Buffers
Patent:
6,157,998 →
Application:
09/054,810 →
Integrated Circuit Having Single Programmable Pull Device Configured to Enable/Disable First Function in Favor of Second Function According to Predetermined Scheme Before/After Reset
Patent:
6,052,746 →
Application:
09/059,818 →
Data Processing System for Processing Vector Data and Method Therefor
Patent:
6,202,130 →
Application:
09/061,975 →
Method and Apparatus for Generating Elements of a Second Vector from a First Vector by Generating Vector Elements of the Second Vector from a Table with Preselected Offset
Patent:
6,334,176 →
Application:
09/062,152 →
Multi-Way Cache Apparatus and Method
Patent:
6,185,657 →
Application:
09/062,571 →
Data Processing System Having Selectable Exception Table Relocation and Method Therefor
Patent:
6,079,015 →
Application:
09/062,952 →
Method of Forming a Semiconductor Device Having a Stacked Capacitor Structure
Patent:
5,998,258 →
Application:
09/064,076 →
Optimization of Ordered Stores on a Pipelined Bus via Self-Initiated Retry
Patent:
6,269,360 →
Application:
09/066,012 →
Multi-Stage Pipelined Data Coalescing for Improved Frequency Operation
Patent:
6,023,737 →
Application:
09/066,014 →
Development Interface for a Data Processor
Patent:
6,145,122 →
Application:
09/067,102 →
Protection Circuit for a Semiconductor Device
Patent:
6,049,119 →
Application:
09/071,323 →
Method and Apparatus for Leveraging History Bits to Optimize Memory Refresh Performance
Patent:
6,167,484 →
Application:
09/076,149 →
Buffer Circuit, Memory Device, and Integrated Circuit for Receiving Digital Signals
Patent:
6,044,036 →
Application:
09/078,159 →
Coupling Noise Reduction Technique Using Reset Timing
Patent:
6,189,133 →
Application:
09/078,786 →
Capped Shallow Trench Isolation and Method of Formation
Patent:
6,146,970 →
Application:
09/084,280 →
Low-Power Decimator for an Oversampled Analog-to-Digital Converter and Method Therefor
Patent:
6,081,216 →
Application:
09/096,049 →
Method and Apparatus for Performing Vector Operation Using Separate Multiplication an Odd and Even Data Elements of Source Vectors
Patent:
6,202,141 →
Application:
09/098,063 →
Data Processor System Having Branch Control and Method Thereof
Patent:
6,401,196 →
Application:
09/100,669 →
Method for Making a Dual-Thickness Gate Oxide Layer Using a Nitride/Oxide Composite Region
Patent:
5,960,289 →
Application:
09/102,267 →
Cmos Semiconductor Devices and Method of Formation
Patent:
6,027,961 →
Application:
09/107,963 →
Data Processing System and Method for Maintaining Translation Lookaside Buffer Tlb Coherency Without Enforcing Complete Instruction Serialization
Patent:
6,119,204 →
Application:
09/108,157 →
Semiconductor Device Having a Metal Containing Layer Overlying a Gate Delectric
Patent:
6,049,114 →
Application:
09/118,877 →
Method for Forming a Semiconductor Device
Patent:
6,218,302 →
Application:
09/121,068 →
Oscillator Amplifier with Frequency Based Digital Multi-Discrete-Level Gain Control and Method of Operation
Patent:
6,121,849 →
Application:
09/121,700 →
Non-Volatile Memory Cell and Method for Manufacturing Same
Patent:
6,232,634 →
Application:
09/124,592 →
Method and Apparatus for Stress Relief in Solder Bump Formation on a Semiconductor Device
Patent:
6,077,726 →
Application:
09/124,720 →
Method and Apparatus for Transferring Data on a Split Bus in a Data Processing System
Patent:
6,240,479 →
Application:
09/127,459 →
System for Address Initialization of Generic Nodes in a Distributed Command and Control System and Method Therefor
Patent:
6,166,653 →
Application:
09/133,226 →
Method for Forming a Semiconductor Device Having a Capacitor Structure
Patent:
5,985,731 →
Application:
09/135,634 →
Linked List Memory and Method Therefor
Method and System for Asynchronous Sample Rate Conversion Using a Noise-Shaped Numerically Control Oscillator
Patent:
6,215,423 →
Application:
09/145,778 →
Wide Shifting in the Vector Permute Unit
Patent:
6,327,651 →
Application:
09/149,466 →
Integrated Circuit Having a Support Structure
Patent:
6,037,668 →
Application:
09/191,353 →
Circuit and Method for Reducing Parasitic Bipolar Effects During Electrostatic Discharges
Patent:
6,329,692 →
Application:
09/201,392 →
Multi-Chip Assembly Having a Heat Sink and Method Thereof
Patent:
6,130,821 →
Application:
09/204,818 →
Process for Forming a Combination Hardmask and Antireflective Layer
Patent:
6,287,951 →
Application:
09/206,715 →
Memory Data Bus Architecture and Method of Configuring Multi- Wide Word Memories
Patent:
6,049,501 →
Application:
09/210,827 →
Sample and Hold Circuit and Method Therefor
Patent:
6,198,314 →
Application:
09/236,064 →
Method and Circuit for Testing an Analog-to-Digital Converter Module on a Data Processing System Having an Intermodule Bus
Patent:
6,297,757 →
Application:
09/248,551 →
Process for Forming Semiconductor Device with Thick and Thin Films
Patent:
6,261,978 →
Application:
09/253,875 →
Method and Apparatus for Extending Fatigue Life of Solder Joints Semiconductor Device
Method and System for a Result Code for a Single-Instruction Multiple-Data Predicate Compare Operation
Patent:
6,282,628 →
Application:
09/256,374 →
Method and System for Bounds Comparator
Patent:
6,298,365 →
Application:
09/256,375 →
Output Buffer Circuit and Method of Operation
Patent:
6,674,304 →
Application:
09/258,378 →
Methods and Systems for Detecting and for Responding to Connection of a Battery to a Logic Device
Patent:
6,487,670 →
Application:
09/261,875 →
Method and Apparatus for Accessing Misaligned Data from Memory in an Icienet Manner
Patent:
6,230,238 →
Application:
09/261,877 →
Method of Forming a Semiconductor Device Barrier Layer
Patent:
6,451,181 →
Application:
09/261,879 →
Motor Controller, Integrated Circuit, and Method of Controlling a Motor
Patent:
6,081,091 →
Application:
09/263,561 →
Circuit and Method for Attenuating Noise in a Data Converter
Patent:
6,137,429 →
Application:
09/265,238 →
Data Processing System Having a Fifo Buffer with Variable Threshold Value Based on Input and Output Data Rates and Data Block Size
Patent:
6,389,489 →
Application:
09/271,215 →
Multiple Load Miss Handling in a Cache Memory System
Patent:
6,269,427 →
Application:
09/271,493 →
Processor Having Vector Processing Capability and Method for Executing a Vector Instruction in a Processor
Patent:
6,324,638 →
Application:
09/282,268 →
Method and Apparatus for Controlling a Full-Duplex Communication System
Patent:
6,381,224 →
Application:
09/282,914 →
Method for Designing a Tiled Memory
Patent:
6,249,475 →
Application:
09/286,186 →
Process for Achieving Full Global Planarization During Cmp of Damascene Semiconductor Structures
Patent:
6,350,690 →
Application:
09/288,646 →
Method of Forming Embedded Dram Structure
Patent:
6,238,967 →
Application:
09/289,915 →
Method for Forming a Copper Layer Over a Semiconductor Wafer
Patent:
6,297,155 →
Application:
09/305,093 →
Method for Preventing Trench Fill Erosion
Patent:
6,271,143 →
Application:
09/306,029 →
Method for Forming a Semiconductor Device
Patent:
6,255,204 →
Application:
09/316,012 →
Method of Formation of Buried Mirror Semiconductive Device
Patent:
6,150,190 →
Application:
09/320,866 →
Low Phase Jitter Clock Signal Generation Circuit
Patent:
6,434,707 →
Application:
09/327,289 →
Method and Apparatus for Processing Interruptible, Multi-Cycle Instructions
Patent:
6,378,022 →
Application:
09/335,105 →
Semiconductor Device and a Process for Designing a Mask
Patent:
6,396,158 →
Application:
09/340,697 →
Multifield Register Having a Selection Field for Selecting a Source of an Information Field
Patent:
6,449,675 →
Application:
09/342,519 →
Packing Variable-Length Code Bits at Fixed Positions
Patent:
6,449,394 →
Application:
09/351,062 →
Method for Forming a Seminconductor Device Using an Etch Stop Layer
Patent:
6,235,603 →
Application:
09/351,442 →
Method for Forming a Semiconductor Device
Patent:
6,171,910 →
Application:
09/358,213 →
Method of Memory Utilization in a Predictive Video Decoder
Process for Forming a Semiconductor Device
Patent:
6,297,173 →
Application:
09/383,238 →
Method for Forming a Semiconductor Device
Patent:
6,313,024 →
Application:
09/394,190 →
Signal Processing Circuit and Method of Operation
Patent:
6,278,394 →
Application:
09/400,257 →
Bit-Wise Conditional Write Method and System for an Mram
Patent:
6,052,302 →
Application:
09/406,425 →
Method of Forming Copper Interconnection Utilizing Aluminum Capping Film
Patent:
6,451,681 →
Application:
09/411,266 →
Method of Identifying an Improved Configuration for a Communication System Using Coding Gain and an Apparatus Therefor
Patent:
6,625,777 →
Application:
09/420,471 →
A Metallic Oxide Semiconductor Gate Electrode Stack Having a Metallic Gate Dielectric Metallic Gate Electrode and a Metallic Arc Layer
Patent:
6,294,820 →
Application:
09/420,600 →
Phase Locked Loop
Patent:
6,242,956 →
Application:
09/425,880 →
Method and Apparatus for a Frequency Modulation Phase Locked Loop
Patent:
6,160,861 →
Application:
09/425,881 →
Data Synchronizer Using a Parallel Handshake Pipeline Wherein Validity Indicators Generate and Send Acknowledgement Signals to a Differeint Clock Domain
Patent:
6,516,420 →
Application:
09/426,265 →
Method and Apparatus for a Calibrated Frequency Modulation Phase Locked Loop
Patent:
6,229,400 →
Application:
09/426,934 →
Linear Capacitor Structure in a Cmos Process
Patent:
6,351,020 →
Application:
09/438,618 →
Method and Apparatus for Decimating an Oversampled Signal
Patent:
6,516,036 →
Application:
09/461,929 →
Circuit and Method for Controlling an Alarm
Patent:
6,346,880 →
Application:
09/468,417 →
Semiconductor Device, a Process for a Semiconductor Device, and a Process for Making a Masking Database
Patent:
6,459,156 →
Application:
09/470,873 →
Semiconductor Device and a Method of Operation the Same
Patent:
6,327,182 →
Application:
09/472,920 →
Circuit And Method For Enabling Semiconductor Device Burn-in
Patent:
6,185,139 →
Application:
09/481,864 →
Method and Apparatus for Testing a Circuit
Patent:
6,532,559 →
Application:
09/491,433 →
Planarization Process to Achieve Improved Uniformity Across Semiconductor Wafers
Patent:
6,472,291 →
Application:
09/492,541 →
Method and Apparatus for Aligning a Waveguide to a Device
Patent:
6,411,758 →
Application:
09/494,457 →
Interconnect structure in a semiconductor device and method of formation
Patent:
6,316,359 →
Application:
09/498,613 →
Data Processing System Having Instruction Folding and Method Thereof
Patent:
6,775,765 →
Application:
09/498,814 →
Debug Controller in a Data Processor and Method Therefor
Patent:
6,591,378 →
Application:
09/507,740 →
Memory Cell and Method for Programming Thereof
Patent:
6,320,784 →
Application:
09/524,916 →
Method of manufacturing a heterojunction bicmos integrated circuit
Patent:
6,461,925 →
Application:
09/539,130 →
Method and Apparatus for Constraint Graph Based Layout Compaction for Integrated Circuits
Patent:
6,434,721 →
Application:
09/541,642 →
Process for operating a semiconductor device
Patent:
6,307,782 →
Application:
09/542,017 →
Method and apparatus for generating an echo clock in a memory
Patent:
6,240,024 →
Application:
09/546,022 →
Electrostatic discharge (ESD) protection circuit
Patent:
6,385,021 →
Application:
09/546,601 →
Mocvd-Grown Emode Higfet Buffer
Patent:
6,429,103 →
Application:
09/548,791 →
Logarithmic gain control circuit and method
Patent:
6,249,170 →
Application:
09/549,835 →
Method and Apparatus for Manufacturing an Interconnect Structure
Patent:
6,429,531 →
Application:
09/551,312 →
System with dll
Patent:
6,294,938 →
Application:
09/552,824 →
Circuit Method for Reducing Parasitic Bipolar Effects During Electrostatic Discharges
Patent:
6,373,104 →
Application:
09/559,354 →
Circuit and method for reducing parasitic bipolar effects during electrostatic discharges
Patent:
6,284,616 →
Application:
09/560,501 →
Process for Depositing a Layer of Materilal on a Substrate
Patent:
6,500,324 →
Application:
09/561,776 →
Performance Monitor System and Method Suitable for Use in an Integrated Circuit
Patent:
6,748,558 →
Application:
09/567,973 →
Process for forming a high-k gate dielectric
Patent:
6,184,072 →
Application:
09/571,588 →
Selective removal of a metal oxide dielectric
Patent:
6,300,202 →
Application:
09/574,732 →
Apparatus for Converting an Analog Signal Utilizing Resistor D/a Converter Precharging
Patent:
6,346,908 →
Application:
09/574,754 →
Process for Forming a Structure
Patent:
6,383,873 →
Application:
09/575,204 →
Multi-channel signaling
Patent:
6,346,832 →
Application:
09/575,257 →
Method and Apparatus for Forming a Semiconductor Device Utilizing a Low Temperature Process
Motion Adaptive Median Filter for Interlace to Progressive Scan Conversion
Patent:
6,414,719 →
Application:
09/579,194 →
Method and Apparatus for Accelerating Communication Between Controllable Devices
Patent:
6,525,501 →
Application:
09/580,292 →
Process for forming a semiconductor device and a process for operating an apparatus
Patent:
6,245,686 →
Application:
09/586,828 →
Massive Parallel Semiconductor Manufacturing Test Process
Patent:
6,433,568 →
Application:
09/588,918 →
Lateral Pnp and Method of Manufacture
Patent:
6,551,869 →
Application:
09/590,461 →
Method of Manufacturing a Semiconductor Component and Semiconductor Component Thereof
Patent:
6,821,829 →
Application:
09/592,349 →
Dual Metal Gate Transistors for Cmos Process
Patent:
6,444,512 →
Application:
09/592,448 →
Processor Having Selective Branch Prediction
Patent:
6,859,875 →
Application:
09/592,449 →
Extended Base Band Multicarrier System
Patent:
6,477,477 →
Application:
09/592,524 →
Method of Forming a Semiconductor Device Having a Buffer
Patent:
6,569,740 →
Application:
09/593,103 →
Data Processing System and Method for a Sector Cache
Patent:
6,766,431 →
Application:
09/594,411 →
Non-volatile programming elements for redundancy and identification in an integrated circuit
Patent:
6,314,023 →
Application:
09/594,504 →
Memory device and method for manufacture
Patent:
6,344,403 →
Application:
09/595,735 →
Process for forming an electrical device
Patent:
6,300,234 →
Application:
09/602,099 →
Capacitive Device and Method of Manufacture
Patent:
6,507,475 →
Application:
09/604,626 →
Semiconductor Device and Method of Formation
Patent:
6,500,750 →
Application:
09/609,523 →
Memory Device Including Isolated Storage Elements That Utilize Hole Conduction and Method Therefor
Patent:
6,400,610 →
Application:
09/610,078 →
Flip Chip Device and Method of Manufacture
Patent:
6,429,046 →
Application:
09/615,865 →
Multi-layer registration control for photolithography processes
Patent:
6,218,200 →
Application:
09/616,152 →
High-side, low-side configurable driver
Patent:
6,348,820 →
Application:
09/617,903 →
Method and Apparatus for Detecting and Compensating Digital Losses in a Communications Network
Patent:
6,785,326 →
Application:
09/632,890 →
Multiple voltage compatible I/O buffer
Patent:
6,323,704 →
Application:
09/633,948 →
Method for decoding a quadrature encoded signal
Patent:
6,300,884 →
Application:
09/633,949 →
Apparatus and method of a low pressure,two-step nucleation tungsten deposition
Patent:
6,309,966 →
Application:
09/639,183 →
Single-To-Differential Buffer Amplifier
Patent:
6,441,688 →
Application:
09/641,990 →
Method of Making Semiconductor Device Having Passive Elements Including Forming Cpacitor Electrode and Resistor from Same Layer of Material
Patent:
6,500,724 →
Application:
09/642,680 →
Method of manufacturing components and component thereof
Patent:
6,310,403 →
Application:
09/652,620 →
Semiconductor Device, Memory Cell, and Processes for Forming Them
Patent:
6,686,633 →
Application:
09/653,338 →
Method of operating a semiconductor device
Patent:
6,330,184 →
Application:
09/659,105 →
Method of Forming an Alternative Ground Contact for a Semiconductor Die
Patent:
6,420,208 →
Application:
09/662,079 →
Semiconductor Structure and Process for Forming a Metal Oxy-Nitride Dielectric Layer
Patent:
6,576,967 →
Application:
09/663,919 →
Selective Sizing of Features to Compensate for Resist Thickness Variations in Semiconductor Devices
Patent:
6,489,083 →
Application:
09/677,496 →
System for Address Initialization of Generic Nodes in a Distributed Command and Control System and Method Therefor
Patent:
6,392,558 →
Application:
09/677,571 →
Method and Apparatus for Coupling Noise Reduction in a Semiconductor Device
Patent:
6,449,195 →
Application:
09/677,697 →
Method of Manufacturing a Semiconductor Component and Semiconductor Component Thereof
Patent:
6,465,297 →
Application:
09/679,861 →
Electronic Component and Method of Manufacture
Patent:
6,630,725 →
Application:
09/684,576 →
Selective Over-Ranging in Folding and Averaging Integrated Circuits
Patent:
6,369,742 →
Application:
09/704,025 →
Semiconductor Device Having a Ball Grid Array and Method Therefor
Device Structure for Storing Charge and Method Therefore
Method and System for Link Fabric Error Detection and Message Flow Control
Patent:
7,106,742 →
Application:
09/758,798 →
Bus Protocol Independent Method and Structure for Managing Transaction Priority, Ordering and Deadlocks in a Multi-Processing System
Multiple Memory Coherence Groups in a Single System and Method Therefor
Method and Apparatus for Maintaining Packet Ordering with Error Recovery Among Multiple Outstanding Packets Between Two Devices
Digital Data System with Link Level Message Flow Control
Patent:
7,031,258 →
Application:
09/758,949 →
Selective Removal of a Metal Oxide Dielectric
Patent:
6,432,779 →
Application:
09/772,632 →
Memory Access with Consecutive Addresses Corresponding to Different Rows
Method and Apparatus for Operating a Communication Bus
Data Processing System with on-Chip Fifo for Storing Debug Information and Method Therefor
High- K Dielectric Film
Method for Forming a High Dielectric Constant Material
Patent:
6,448,192 →
Application:
09/835,770 →
Method for making a hafnium-based insulating film
Patent:
6,348,386 →
Application:
09/836,668 →
Integrated Circuit Structure and Method Therefore
Optical Device and Method Therefor
Method for Making Semiconductor Device
Patent:
6,465,853 →
Application:
09/851,206 →
Method and Apparatus for Controlling Current Demand in an Integrated Circuit
Recording of result information in a built-in self-test circuit and method therefor
Patent:
6,347,056 →
Application:
09/859,333 →
Semiconductor Device and a Method Therefor
Test Access Mechanism for Supporting a Configurable Built-in Self-Test Circuit and Method Thereof
Method of Forming an Integrated Circuit Device Using Dummy Features and Structure Thereof
Integration of Two Memory Types on the Same Integrated Circuit
First-In, First-Out Memory System Having Both Simultaneous and Alternating Data Access and Method Thereof
Method and Apparatus for Forming a Pattern on an Integrated Circuit Using Differing Exposure Characteristics
Component Having a Filter
Semiconductor Device and Method of Formation
Method for Adding Features to a Design Layout and Process for Designing a Mask
Selective Metal Oxide Removal
Active Bias Circuit
Patent:
6,492,874 →
Application:
09/918,015 →
Dielectric Between Metal Structures and Method Therefor
Data Processing System Having an Adaptive Priority Controller
Method of Forming a Pattern on a Semiconductor Wafer Using an Attenuated Phase Shifting Reflective Mask
Low Power Cyclic a/D Converter
Patent:
6,535,157 →
Application:
09/949,245 →
Method of Forming a Semiconductor Device Having Conductive Bumps Without Using Gold
Patent:
6,489,229 →
Application:
09/949,454 →
Method of Forming a Bond Pad and Structure Thereof
Key Stream Cipher Device
System Having User Programmable Addressing Modes and Method Therefor
Packaged Semiconductor with Multiple Rows of Bond Pads and Method Therefor
Patent:
6,476,506 →
Application:
09/966,584 →
Method for Forming a Semiconductor Device for Detecting Light
Optical Device and Method Therefor
Transistor Metal Gate Structure That Minimizes Non-Planarity Effects and Method of Formation
Patent:
6,423,619 →
Application:
09/997,899 →
Interrupt Processing in a Data Processing System
Semiconductor Power Device and Method of Formation
Substrate Contact in Soi and Method Therefor
High Frequency Signal Isolation in a Semiconductor Device
Semiconductor Component and Method of Operation
Rsd Analog to Digital Converter
Patent:
6,489,914 →
Application:
10/005,275 →
Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
Packaged Integrated Circuit and Method Therefor
System for Providing a Calibrated Clock and Methods Thereof
Method and Apparatus for the Automatic Synchronization of Dynamic Angular and Time Domain Control Systems
Method of Forming Body-Tied Silicon on Insulator Semiconductor Device
Deterministic Prediction in an Image Processing System
Method and Apparatus for Detecting a Stall Condition in a Stepping Motor
Hysteresis Reduced Sense Amplifier and Method of Operation
Semiconductor Apparatus
Chemistry for Etching Quaternary Interface Layers on Ingaasp Mostly Formed Between Gaas and Inxga(1-X)P Layers
Wire Bond-Less Electronic Component for Use with an External Circuit and Method of Manufacture
Method and Apparatus for Signal Detection
Enable Propagation Controller
Step-Down Clock Control and Method for Improving Convergence for a Digitally Controlled Self-Calibrating Vco
Patent:
6,496,556 →
Application:
10/047,189 →
Article Comprising an Oxide Layer on a Gaas-Based Semiconductor Structure and Method of Forming Same
Method and System of Data Processor Design by Sensitizing Logical Difference
Interface Between Programming Languages and Method Therefor
Semiconductor Device Having a Fuse and Method of Forming Thereof
Process and Apparatus for Disengaging Semiconductor Die from an Adhesive Film
Method for Processing Multiple Semiconductor Devices for Test
Stacked Die Semiconductor Device
Method for Manufacturing a Lithographic Reticle for Transferring an Integrated Circuit Design to a Semiconductor Wafer
High Frequency Semiconductor Device and Method of Manufacture
Multi-Row Leadframe
Semiconductor Device Having a Wire Bond Pad and Method Therefor
Transistor with Layered High-K Gate Dielectric and Method Therefor
High K Dielectric Film
Integrated Circuit Security and Method Therefor
Integrated Circuit Device and Method Therefor
Semiconductor Component Having High Voltage Mosfet and Method of Manufacture
Digital Color Image Pre-Processing
Automatic White Balance for Digital Imaging
System and Method for Cache External Writing
Data Prefetching Apparatus in a Data Processing System and Method Therefor
Apparatus and Resonant Circuit Employing a Varactor Diode in Parallel with a Transmission Line and Method Thereof
Digital-To- Analog Conversion with Current Path Exchange During Clock Phases
Patent:
6,621,438 →
Application:
10/135,782 →
Hbt Linearizer and Power Booster
Under Bump Metallurgy Structural Design for High Reliability Bumped Packages
Trench Mos Resurf Super-Junction Devices
Lithography Correction Method and Device
Dual Metal Gate Transistors for Cmos Process
System and Method for Regulating a Power System with Feedback Using Current Sensing
Methods and Devices for Controlling Stepper Motors
Method and Apparatus for Affecting a Portion of an Integrated Circuit
Method of Forming a Semiconductor Device in a Semiconductor Layer and Structure Thereof
System and Method for a Data Processing System Having Multiple Register Contexts That Include Context Control Information
Dma Controller
System, Apparatus and Method for Voltage to Current Conversion
Bipolar Junction Transistor Structure with Improved Current Gain Characteristics
Reduced Power Analog-to-Digital Converter and Method Thereof
Method and Apparatus for Pure Delay Estimation in a Communication System
Method and Apparatus for Performing Adaptive Filtering
Monitoring and Control of an Adaptive Filter in a Communication System
Method and Apparatus for Tone Indication
Program and Erase in a Thin Film Storage Non-Volatile Memory
Advanced Rf Enhancement-Mode Fets with Improved Gate Properties
Bias Control for Hbt Power Amplifiers
Sense Amplifier Incorporating a Symmetric Midpoint Reference
Patent:
6,621,729 →
Application:
10/185,224 →
Three Input Sense Amplifier and Method of Operation
Patent:
6,580,298 →
Application:
10/186,363 →
Reduced Peak Emi Bus Using Variable Bit Rate Spreading
Method and Apparatus for Skewing Data with Respect to Command on a Ddr Interface
Variable Length Decoder
Patent:
6,667,701 →
Application:
10/196,532 →
Multi-Bit Non-Volatile Memory Cell and Method Therefor
Symbol Timing Tracking and Method Therefor
Simplification of Ball Attach Method Using Super-Saturated Fine Crystal Flux
Method of Making a Mount for Electronic Devices
Capped Dual Metal Gate Transistors for Cmos Process and Method for Making the Same
Test System for Device and Method Thereof
Field Plate Transistor with Reduced Field Plate Resistance
Field Effect Transistor and Method of Manufacturing Same
Method of Forming a Rim Phase Shifting Mask and Using the Rim Phase Shifting Mask to Form a Semiconductor Device
Electrostatic Discharge Protection Circuitry and Method of Operation
Process for Depositing a Layer of Material on a Substrate and a Plating System
Method for Forming a Dual Gate Oxide Device Using a Metal Oxide and Resulting Device
Semiconductor Fabrication Process for Modifying the Profiles of Patterned Features
Semiconductor Device for Reducing Photovolatic Current
Closed Loop Current Control Circuit and Method Thereof
System and Circuit for Controlling Well Biasing and Method Thereof
Method of Forming Nanocrystals in a Memory Device
Removable Media Storage System with Memory for Storing Operational Data
Oscillator Circuit Having Reduced Layout Area and Lower Power Supply Transients
Dual Metal Gate Transistors for Cmos Process
Active Current Bias Network for Compensating Hot-Carrier Injection Induced Bias Drift
Semiconductor Device Having Passive Elements and Method of Making Same
Semiconductor Component and Method of Operating Same
Patent:
6,703,895 →
Application:
10/256,820 →
Photomask Having Line End Phase Anchors
Non-Volatile Memory Device and Method for Forming
Non-Volatile Memory Device Having an Anti-Punch Through (Apt) Region
Patent:
6,713,812 →
Application:
10/267,199 →
Method for Eliminating Voiding in Plated Solder
Band Switchable Voltage Controlled Oscillator with Substantially Constant Tuning Range
Patent:
6,674,333 →
Application:
10/271,828 →
Carrier Injection Protection Structure
Erase of a Memory Having a Non-Conductive Storage Medium
Cross Coupled Cascode Voltage Controlled Oscillator
Patent:
6,700,451 →
Application:
10/281,591 →
Sense Amplifier Bias Circuit for a Memory Having at Least Two Distinct Resistance States
Patent:
6,700,814 →
Application:
10/283,622 →
Split-Gate Thin-Film Storage Nvm Cell
Digital Image Processing Using White Balance and Gamma Correction
Multiple Gate Transistor Employing Monocrystalline Silicon Walls
Automatic Exposure Control System for a Digital Camera
Semiconductor Fabrication Process Using Transistor Spacers of Differing Widths
Floating Resurf Ldmosfet and Method of Manufacturing Same
Gate Voltage Reduction in a Memory Read
Reflective Mask Useful for Transferring a Pattern Using Extreme Ultraviolet (Euv) Radiation and Method of Making the Same
Storage Circuit Having Single-Ended Write Circuitry
Low Profile Semiconductor Device Having Improved Heat Dissipation
Low Voltage Detection System
Tone Detector and Method Therefor
Hybrid N+ and P+ Gate-Doped Voltage Variable Capacitors to Improve Linear Tuning Range in Voltage Controlled Oscillators
Controlled Bias Current Buffer and Method Thereof
Patent:
6,707,339 →
Application:
10/301,992 →
Film Depositon on a Semiconductor Wafer
Structure to Reduce Signal Cross-Talk Through Semiconductor Substrate for System on Chip Applications
Method and Apparatus for Establishing a Reference Voltage in a Memory
Technique for Sensing the State of a Magneto-Resistive Random Access Memory
Thin Gaas Die with Copper Back-Metal Structure
Non-Volatile Memory Architecture and Method Thereof
Method of Accessing Memory and Device Thereof
Transient Detection Circuit
Miniature Moldlocks for Heatsink or Flag for an Overmolded Plastic Package
Packaged Integrated Circuit Having Wire Bonds and Method Therefor
Structure and Method of Thermally Protecting Power Devices for Airbag Deployment
Method and Apparatus for Translating Detected Wafer Defect Coordinates to Reticle Coordinates Using Cad Data
Vertical Mosfet with Asymmetric Gate Structure
Patent:
6,686,245 →
Application:
10/324,787 →
Low Voltage Current Sources/Current Mirrors
Method for Forming a Passivation Layer for Air Gap Formation
Method for Providing a Dummy Feature and Structure Thereof
Methods and Apparatus for Detecting Out-of-Range Signals in an Analog-to-Digital Converter
Patent:
6,741,194 →
Application:
10/328,360 →
Flip-Chip Structure and Method for High Quality Inductors and Transformers
Electronic Component and Method of Manufacturing Same
Patent:
6,734,524 →
Application:
10/335,030 →
Offset Compensated Differential Amplifier
Patent:
6,750,704 →
Application:
10/340,335 →
Semiconductor Fabrication Method for Making Small Features
Method of Patterning Photoresist on a Wafer Using a Transmission Mask with a Carbon Layer
Integration of Two Memory Types on the Same Integrated Circuit
Electrostatic Discharge Circuit and Method Therefor
Electrostatic Discharge Circuit and Method Therefor
High Efficiency Electrical Switch and Dc-Dc Converter Incorporating Same
Dielectric Between Metal Structures and Method Therefor
Metal Reduction in Wafer Scribe Area
A Method of Forming an Arc Layer for a Semiconductor Device
Digital Tuning Scheme for Continuous-Time Sigma Delta Modulation
Patent:
6,693,572 →
Application:
10/358,055 →
Low Voltage Nmos-Based Electrostatic Discharge Clamp
Radical Oxidation and/or Nitridation During Metal Oxide Layer Deposition Process
Integrated Circuit Well Bias Circuity
Electronic Component and Method of Manufacturing Same
Method of Manufacturing a Semiconductor Component
Variable Refresh Control for a Memory
Patent:
6,778,457 →
Application:
10/369,985 →
Memory Having Variable Refresh Control and Method Therefor
Multi-Die Semiconductor Package
Wirebonding Insulated Wire
Semiconductor Device and Method Thereof
Amplifier Apparatus and Method Thereof
Method of Patterning Photoresist on a Wafer Using an Attenuated Phase Shift Mask
Method of Patterning Photoresist on a Wafer Using a Reflective Mask with a Multi-Layer Arc
Method and Structure for Low-K Dielectric Constant Applications
Patent:
6,774,053 →
Application:
10/384,350 →
Method for Forming a Low-K Dielectric Structure on a Substrate
Semiconductor Package with Multiple Sides Having Package Contacts
Semiconductor Component
Write Operation for Capacitorless Ram
Patent:
6,714,436 →
Application:
10/393,053 →
Multiprocessor System Having a Shared Main Memory Accessible by All Processor Units
Method for Fabricating Dual-Metal Gate Device
Frequency Generating Device and Method Thereof
Method for Forming an Esd Protection Device
Integrated Vertical Stack Capacitor
Patent:
6,765,778 →
Application:
10/407,701 →
Integrated Circuit Die I/O Cells
Patent:
6,717,270 →
Application:
10/409,766 →
Process for Forming Dual Metal Gate Structures
Patent:
6,790,719 →
Application:
10/410,043 →
Electronic Component and Method of Manufacturing Same
Semiconductor Component and Method of Manufacturing Same
Patent:
6,683,370 →
Application:
10/417,992 →
Circuit Device with at Least Partial Packaging and Method for Forming
Circuit Device with at Least Partial Packaging, Exposed Active Surface and a Voltage Reference Plane
Semiconductor Component Having First Surface Area for Electrically Coupling to a Semiconductor Chip and Second Surface Area for Electrically Coupling to a Substrate, and Method of Manufacturing Same
Integrated circuit with a transistor over an interconnect layer
Process for Forming a Metal Oxy-Nitride Dielectric Layer by Varying the Flow Rate of Nitrogen into the Chamber
Non-Volatile Memory Having a Bias on the Source Electrode for Hci Programming
Inverted Isolation Formed with Spacers
Semiconductor Device and Method Utilizing Variable Mode Control with Block Ciphers
Capping Layer for Reducing Amorphous Carbon Contamination of Photoresist in Semiconductor Device Manufacture; and Process for Making Same
Patent:
7,109,101 →
Application:
10/430,711 →
Prefetch Control in a Data Processing System
Balanced Radio Frequency Power Amplifier with Temperature Compensation
Method and Apparatus for Interconnecting Portions of Circuitry Within a Data Processing System
Memory with Charge Storage Locations and Adjacent Gate Structures
Electromagnetic Band Gap Microwave Filter
Semiconductor Power Device with Shear Stress Compensation
High Impedance Radio Frequency Power Plastic Package
Method and Apparatus for Controlling a Voltage Controlled Oscillator
Semiconductor Package Having Optimized Wire Bond Positioning
Patent:
6,812,580 →
Application:
10/457,632 →
Body-Tied Silicon on Insulator Semiconductor Device and Method Therefor
Circuit for Electrostatic Discharge Protection
Method and Computer Program Product for Generation of Bus Functional Models
Transmitter for a Controlled-Shape Switched Signal on a Communication Line
Apparatus and Method for Power Management in a Tire Pressure Monitoring System
System Node and Method for Providing Media Arbitration
Arrangement, Phase Locked Loop and Method for Noise Shaping in a Phase-Locked Loop
Communicating Conversational Data Between Signals Between Terminals Over a Radio Link
Keypad Signal Input Apparatus
Network Node
High Frequency Thin Film Electrical Circuit Element
Power Amplifier Module and a Time Division Multiple Access Radio
Decoupling Technique for Optical Disk Drive Optical Pickup Units
Chemical Mechanical Polish (Cmp) Conditioning-Disk Holder
Memory with Multiple State Cells and Sensing Method
Semiconductor Device Having a Wire Bond Pad and Method Therefor
Radio Frequency Power Transistor Avalanche Breakdown Detection Circuit and Method Therefor
Patent:
6,825,727 →
Application:
10/608,602 →
Variable Gate Bias for a Reference Transistor in a Non-Volatile Memory
Method for Forming a Non-Volatile Memory Having a Reference Transistor
Polishing System Having a Carrier Head with Substrate Presence Sensing
Robust Lcd Controller
Semiconductor Component and Method of Manufacturing
Semiconductor Component Comprising Leadframe, Semiconductor Chip and Integrated Passive Component in Vertical Relationship to Each Other
Power Consumption Estimation
Micellar Technology for Post-Etch Residues
Method and Apparatus for Performing Failure Analysis with Fluorescence Inks
Method and Apparatus for Selecting Cache Ways Available for Replacement
Prefetch Control in a Data Processing System
Crossbar Switch That Supports a Multi-Port Slave Device and Method of Operation
Multibit Rom Cell and Method Therefor
Two Port Voltage Controlled Oscillator for Use in Wireless Personal Area Network Synthesizers
Method of forming a bond pad including removing a portion of a protective layer
Heterojunction Bipolar Transistor with Monolithically Integrated Junction Field Effect Transistor and Method of Manufacturing Same
Electromechanical Resonator and Method of Operating Same
Wirebonding Insulated Wire and Capillary Therefor
Multiplexing of Digital Signals at Multiple Supply Voltages in an Integrated Circuit
Controlling Attenuation During Echo Suppression
Arbiter Having Programmable Arbitration Points for Undefined Length Burst Accesses and Method
Level Shifter
Method of Forming a Semiconductor Package and Structure Thereof
Method and System for Processing a Loop of Instructions
Method and Circuitry for Preserving a Logic State
Patent:
6,850,105 →
Application:
10/675,397 →
Method and System for Reducing Power Consumption in a Cache Memory
Semiconductor Structure with Different Lattice Constant Materials and Method for Forming the Same
Patent:
6,831,350 →
Application:
10/677,844 →
Electrostatic Discharge Protection Circuit and Method of Operation
Method and System for Direct Access to a Non-Memory Mapped Device Memory
Attenuated Phase Shift Mask for Extreme Ultraviolet Lithography and Method Therefore
Amplifier Circuit
Semiconductor Device and Method of Forming the Same
Domino Comparator Capable for Use in a Memory Array
Semiconductor Device with Magnetically Permeable Heat Sink
Method for Forming a Microwave Field Effect Transistor with High Operating Voltage
Patent:
6,867,078 →
Application:
10/716,955 →
Inductive Device Including Bond Wires
Hardware for Performing an Arithmetic Function
Method and Apparatus for Dynamically Inserting Gain in an Adaptive Filter System
Land Grid Array Packaged Device and Method of Forming Same
Method and Apparatus to Implement Dc Offset Correction in a Sigma Delta Converter
Method for Reducing Corrosion of Metal Surfaces During Semiconductor Processing
Low-Power Compiler-Programmable Memory with Fast Access Timing
Method for Elimination of Excessive Field Oxide Recess for Thin Si Soi
Integrated Circuit Device and Method Therefor
Slotted Planar Power Conductor
Method and Apparatus for Demodulating a Received Signal Within a Coded System
Circuit and Method for Supplying an Electrical a.C. Load
Signal Generation Power Management Control System for Portable Communications Device and Method of Using Same
Method for Etching a Quartz Layer in a Photoresistless Semiconductor Mask
Non-Volatile Memory Device with Improved Data Retention and Method Therefor
Autonomous Memory Checker for Runtime Security Assurance and Method Therefore
Multiple Burst Protocol Device Controller
Selective Tone Event Detector and Method Therefor
Self-Calibrating Oscillator System
Detecting Overcurrents in a Switching Regulator Using a Voltage Dependent Reference
Electrostatic Discharge Protection Device and Method Therefore
Load Board with Embedded Relay Tracker
Transistor with Reduced Gate-to-Source Capacitance and Method Therefor
Method and Apparatus for Doherty Amplifier Biasing
Method for Forming a Semiconductor Device Having a Notched Control Electrode and Structure Thereof
State Retention Within a Data Processing System
Method of Manufacturing a Wire Bond-Less Electronic Component for Use with an External Circuit
Motion Sensing for Tire Pressure Monitoring
A Method of Making a High Quality Thin Dielectric Layer
Method of Semiconductor Fabrication Incorporating Disposable Spacer into Elevated Source/Drain Processing
Circuit for Performing Voltage Regulation
Semiconductor Process and Integrated Circuit Having Dual Metal Oxide Gate Dielectric with Single Metal Gate Electrode
Patent:
6,897,095 →
Application:
10/843,850 →
Packaged Ic Using Insulated Wire
Decoupled Complementary Mask Patterning Transfer Method
Automatic Hidden Refresh in a Dram and Method Therefor
Method for Forming a Semiconductor Device Having a Silicide Layer
Memory with Serial Input/Output Terminals for Address and Data and Method Therefor
Temperature Compensated on-Chip Bias Circuit for Linear Rf Hbt Power Amplifiers
Memory with Recessed Devices
Method for Treating a Semiconductor Surface to Form a Metal-Containing Layer
Memory Device with a Data Hold Latch
Method to Reduce Impurity Elements During Semiconductor Film Deposition
Reflective Mask Useful for Transferring a Pattern Using Extreme Ultra Violet (Euv) Radiation and Method of Making the Same
Arrangement and Method for Digital Delay Line
Method for Making a Semiconductor Device with Reduced Spacing
Variable Refresh Control for a Memory
Lead Solder Indicator and Method
Article Comprising an Oxide Layer on a Gaas-Based Semiconductor Structure and Method of Forming Same
Method and Apparatus for Selectively Optimizing Interpreted Language Code
Schottky Device and Method of Forming
Method of Passivating Oxide/Compound Semiconductor Interface
Semiconductor Structures and Methods of Fabricating Semiconductor Structures Comprising Hafnium Oxide Modified with Lanthanum, a Lanthanide-Series Metal, or a Combination Thereof
Methods of Fabricating Semiconductor Structures Comprising Epitaxial HF3SI2 Layers
Patent:
6,852,588 →
Application:
10/883,181 →
Memory Having Variable Refresh Control and Method Therefor
Memory Row/Column Replacement in an Integrated Circuit
Method of Assembling a Semiconductor Component and Apparatus Therefor
Memory with Fault Tolerant Reference Circuitry
Automatic Gain Control for an Adaptive Finite Impulse Response and Method Therefore
Method of Forming a Semiconductor Device and Structure Thereof
Interfacial Layer for Use with High K Dielectric Materials
Memory Bit Line Segment Isolation
Method of Discharging a Semiconductor Device
Method and Apparatus for Performance Enhancement in an Asymmetrical Semiconductor Device
Method and Apparatus for Mobility Enhancement in a Semiconductor Device
Recessed Semiconductor Device
Variable Impedance Output Buffer
Applications of a High Impedance Surface
Frequency Selective High Impedance Surface
Programming and Erasing Structure for an Nvm Cell
Method and Apparatus for Modifying an Information Unit Using an Atomic Operation
Open Loop Motor Parking Method and System
System and method for fetching information in response to hazard indication information
Method of Forming a Semiconductor Device Having a Metal Layer
Mram Sense Amplifier Having a Precharge Circuit and Method for Sensing
Programming and Erasing Structure for a Floating Gate Memory Cell and Method of Making
Programming and Erasing Structure for a Floating Gate Memory Cell and Method of Making
Semiconductor Device Having a Gate with a Thin Conductive Layer
Deposition and Patterning of Boron Nitride Nanotube Ild
Method of Forming a Semiconductor Device Having a Dielectric Layer with High Dielectric Constant
Method and Apparatus for Protecting an Integrated Circuit from Erroneous Operation
Non-Volatile Memory Having a Reference Transistor
Double Gate Device Having a Heterojunction Source/Drain and Strained Channel
Plasma Enhanced Nitride Layer
Device and a Method for Biasing a Transistor That Is Connected to a Power Converter
Apparatus and Method for Providing Information to a Cache Module Using Fetch Bursts
Integrated Circuit Fuses Having Corresponding Storage Circuitry
Isolation Trench Perimeter Implant for Threshold Voltage Control
Method for Forming a Multi-Bit Non-Volatile Memory Device
Virtual Ground Memory Array and Method Therefor
Integration of Multiple Gate Dielectrics by Surface Protection
System and Method for Cache External Writing and Write Shadowing
Logic Circuitry
Radio Frequency Power Amplifier
Manufacturing Method to Construct Semiconductor-on-Insulator with Conductor Layer Sandwiched Between Buried Dielectric Layer and Semiconductor Layers
Transconductance Amplifier
Semiconductor Device Having Trench Isolation for Differential Stress and Method Therefor
Semiconductor Structure Having a Metallic Buffer Layer and Method for Forming
Power Amplifier Saturation Detection and Operation at Maximum Power
Method of Integrating Optical Devices and Electronic Devices on an Integrated Circuit
Method of Forming a Semiconductor Device
Method of Forming a Semiconductor Device
Calibration Device for a Phased Locked Loop Synthesiser
Integrated Circuit Having a Non-Volatile Memory with Discharge Rate Control and Method Therefor
Word Line Driver Circuit for a Static Random Access Memory and Method Therefor
Semiconductor Process for Forming Stress Absorbent Shallow Trench Isolation Structures
Temperature Based Dram Refresh
Low Voltage Nmos-Based Electrostatic Discharge Clamp
Design Analysis Tool and Method for Deriving Correspondence Between Storage Elements of Two Memory Models
Compact Radio Frequency Harmonic Filter Using Integrated Passive Device Technology
Electronic Device Including Dielectric Layer, and a Process for Forming the Electronic Device
Method and Apparatus for Providing Structural Support for Interconnect Pad While Allowing Signal Conductance
Sram Having Improved Cell Stability and Method Therefor
System and Method for Flicker Detection in Digital Imaging
Clocked Ramp Apparatus for Voltage Regulator Softstart and Method for Softstarting Voltage Regulators
Methods and Apparatus Having Wafer Level Chip Scale Package for Sensing Elements
Semiconductor Fabrication Process Employing Stress Inducing Source Drain Structures with Graded Impurity Concentration
Novel Gate Dielectric and Metal Gate Integration
Electronic Device Comprising a Gate Electrode Including a Metal-Containing Layer Having One or More Impurities and a Process for Forming the Same
Integrated Circuit with Programmable-Impedance Output Buffer and Method Therefor
Stacked Die Semiconductor Device
Parallel Path Alignment Method and Apparatus
Method and System for Indicating Zero-Crossings of a Signal in the Presence of Noise
Method and Circuit for Maintaininig I/O Pad Characteristics Across Different I/O Supply Voltages
Voltage Regulator Having Improved Ir Drop
Hybrid-Fet and Its Application as Sram
Method for Manufacturing Thin Gaas Die with Copper-Back Metal Structures
I/O Cell Esd System
Processes for Forming Electronic Devices Including a Semiconductor Layer
Processes for Testing a Region for an Analyte and a Process for Forming an Electronic Device
Methods for Programming a Floating Body Nonvolatile Memory
Delay Circuitry and Method Therefor
Method for Determining Programmable Coefficients to Replicate Frequency and Supply Voltage Correlation in an Integrated Circuit
Audio Modulated Light System for Personal Electronic Devices
Method of Forming a Semiconductor Device and an Optical Device and Structure Thereof
Integrated Circuit Storage Element Having Low Power Data Retention and Method Therefor
Integrated Circuit Having a Low Power Mode and Method Therefor
Semiconductor Structures and Methods for Fabricating Semiconductor Structures Comprising High Dielectric Constant Stacked Structures
Compact Non-Volatile Memory Array with Reduced Disturb
Processes for Forming Electronic Devices Including Non-Volatile Memory
System and Method for Human Body Fall Detection
Differential Nulling Avalanche (Dna) Clamp Circuit and Method of Use
Digital Time Constant Tracking Technique and Apparatus
Virtual Machine Extended Capabilities Using Application Contexts in a Resource-Constrained Device
Multi-Gate Enhancement Mode Rf Switch and Bias Arrangement
Method of Forming a Semiconductor Device Having Asymmetric Dielectric Regions and Structure Thereof
System for Integrated Data Integrity Verification and Method Thereof
System and Method for Roll-Off Correction in Image Processing
System and Method for Bad Pixel Replacement in Image Processing
Transitional Dielectric Layer to Improve Reliability and Performance of High Dielectric Constant Transistors
Method and apparatus facilitating multi mode interfaces
Methods and Apparatus for Synchronizing Data Transferred Across a Multi-Pin Asynchronous Serial Interface
Apparatus for Current Sensing
Patent:
7,102,365 →
Application:
11/097,593 →
Flip-Flop Circuit Having Low Power Data Retention
Clock Delay Compensation Circuit
Voltage Controlled Oscillator with Gain Control
System, Method and Program Product for Well-Bias Set Point Adjustment
Method and Apparatus for Powering and Loading Software into a Battery-Less Electronic Device
Method of Forming an Electronic Device
Method of Tiling Analog Circuits
Phemt with Barrier Optimized for Low Temperature Operation
Eye Center Determination System and Method
Eye Center Retraining System and Method
Pecvd Nitride Film
Method of Forming a Substrateless Semiconductor Package
Semiconductor Device and Method for Regional Stress Control
Semiconductor Device Having a Plurality of Different Layers and Method Therefor
Electrostatic Discharge Circuit and Method Therefor
Self Correcting Suppression of Threshold Voltage Variation in Fully Depleted Transistors
Front-End Method for Nicam Encoding
Nicam Encoder Featuring Synchronization of a Nicam Processor with Front-End Input and Output Sections
Patent:
7,109,906 →
Application:
11/118,211 →
Logic Threshold Acquisition Circuits and Methods Using Reversed Peak Detectors
High Bandwidth Resistor
Integrated Circuit Having a Non-Volatile Memory with Discharge Rate Control and Method Therefor
Prefetching Using Hashed Program Counter
Method and Apparatus for Low Voltage Write in a Static Random Access Memory
High Voltage Field Effect Device and Method
State Retention Power Gating Latch Circuit
Method of Tiling Analog Circuits That Include Resistors and Capacitors
Integrated Circuit with Multiple Independent Gate Field Effect Transistor (Migfet) Rail Clamp Circuit
Storage Circuit and Method Therefor
Non-Volatile Fuse Circuit
Self-Aligning Resonator Filter Circuit and Wideband Tuner Circuit Incorporating Same
Article Comprising an Oxide Layer on a Gaas-Based Semiconductor Structure and Method of Forming Same
Reverse Ald
Semiconductor Package and Method for Forming the Same
Semiconductor Device and Method of Manufacture
Method of Accessing Information and System Therefor
Semiconductor Device and Method of Manufacture
Semiconductor Device and Method of Manufacture
Drive Arrangement for Activating a Car Safety Device Activation Element
In-Situ Nitridation of High-K Dielectrics
Circuit Device with at Least Partial Packaging and Method for Forming
Method for Forming an Electronic Device
Multi-Channel Analog to Digital Converter
Patent:
7,064,700 →
Application:
11/154,405 →
Programmable Dual Input Switched-Capacitor Gain Stage
Area Diode Formation in Soi Application
Vertical Diode Formation in Soi Application
Chemical Die Singulation Technique
Method and Apparatus for Maintaining Topographical Uniformity of a Semiconductor Memory Array
Method of Making a Metal Gate Semiconductor Device
Integrated Circuit Well Bias Circuitry
Antifuse Element and Method of Manufacture
Tunable Antifuse Element and Method of Manufacture
Source Side Injection Storage Device and Method Therefor
Source Side Injection Storage Device with Control Gates Adjacent to Shared Source/Drain and Method Therefor
Semiconductor Fabrication Process for Integrating Formation of Embedded Nonvolatile Storage Device with Formation of Multiple Transistor Device Types
Method of Manufacturing a Passive Integrated Matching Network for Power Amplifiers
Cr-Capped Chromeless Phase Lithography
Method of Manufacturing a Semiconductor Component
Nonvolatile Storage Array with Continuous Control Gate Employing Hot Carrier Injection Programming
Electronic Device Including Gate Lines, Bit Lines, or a Combination Thereof
Process for Operating an Electronic Device Including a Memory Array and Conductive Lines
Electronic Device Including Discontinuous Storage Elements
Semiconductor Devices and Method of Fabrication
Power Amplifier with Vswr Detection and Correction Feature
Packaged Integrated Circuit with Enhanced Thermal Dissipation
Multiport Single Transistor Bit Cell
Diffusion Barrier for Nickel Silicides in a Semiconductor Fabrication Process
Fabrication of Three Dimensional Integrated Circuit Employing Multiple Die Panels
Method for Forming Uniaxially Strained Devices
Data Signal System
Clock Tree Adjustable Buffer
Method of Accessing Memory via Multiple Slave Ports
Management of Security Features in a Communication Network
Method for Forming Floating Gates Within Nvm Process
Digitally Programmable Capacitor Array
Nonvolatile Memory Cell Programming
Semiconductor Devices Employing Poly-Filled Trenches
Semiconductor Device with Magnetically Permeable Heat Sink
Radiation Shielded Module and Method of Shielding Microelectronic Devices
Patent:
7,145,084 →
Application:
11/215,888 →
Polynomial Generation Method for Circuit Modeling
Memory with Robust Data Sensing and Method for Sensing Data
Patent:
7,158,432 →
Application:
11/218,135 →
Grooved Platen with Channels or Pathway to Ambient Air
Platen Endpoint Window with Pressure Relief
Binary Stream Switching Controlled Modulus Divider for Fractional Frequency Synthesis
Method and Apparatus for Protecting Rf Power Amplifiers
Floating Point Normalization and Denormalization
Semiconductor Fabrication Process Including Silicide Stringer Removal Processing
Iii-V Compound Semiconductor Heterostructure Mosfet Device
Process of Making a Iii-V Compound Semiconductor Heterostructure Mosfet
Linear Voltage Controlled Variable Attenuator with Linear Db/V Gain Slope
Method of Forming an Oxide Layer on a Compound Semiconductor Structure
Laterally Grown Nanotubes and Method of Formation
Method of Making a Multi-Bit Non-Volatile Memory (Nvm) Cell and Structure
Multiple Fin Formation
Method of Transferring a Thin Crystalline Semiconductor Layer
Patent:
7,153,761 →
Application:
11/243,010 →
Semiconductor Device Having Nano-Pillars and Method Therefor
Programmable Fuse with Silicon Germanium
Integrated Fault Detector Circuit
Signal Converters with Multiple Gate Devices
Voltage Controlled Oscillator Having Digitally Controlled Phase Adjustment and Method Therefor
Agc for Narrowband Receivers
Printing of Design Features Using Alternating Psm Technology with Double Mask Exposure Strategy
Design-For-Test Circuit for Low Pin Count Devices
Semiconductor Structure and Method of Manufacture
Semiconductor Structure and Method of Assembly
Plastic Packaged Device with Die Interface Layer
System and Method for Memory Array Access with Fast Address Decoder
Multiple Device Types Including an Inverted-T Channel Transistor and Method Therefor
Method of Making an Inverted-T Channel Transistor
Non-Volatile Memory Cell Array for Improved Data Retention and Method of Operating Thereof
Methods of Generating Planar Double Gate Transistor Shapes and Data Processing System Readable Media to Perform the Methods
Methods of Generating Planar Double Gate Transistor Shapes
Semiconductor Structure with Reduced Gate Doping and Methods for Forming Thereof
Data Scan Mechanism
Electronic Assembly Having Graded Wire Bonding
Method and Apparatus for Testing a Semiconductor Structure Having Top-Side and Bottom-Side Connections
Method for Forming Multi-Layer Bumps on a Substrate
Semiconductor Device and Method for Forming the Same
Electrostatic Discharge (Esd) Protection Circuit for Multiple Power Domain Integrated Circuit
Nanocrystal Bitcell Process Integration for High Density Application
Detecting a Data Frame
Fine Pitch Interconnect and Method of Making
Method of Patterning Photoresist on a Wafer Using a Reflective Mask with a Multi-Layer Arc
Electronic Device Including a Transistor Structure Having an Active Region Adjacent to a Stressor Layer and a Process for Forming the Electronic Device
Resource efficient video processing via prediction error computational adjustments
Memory with Charge Storage Locations
Barrier for Use in 3-D Integration of Circuits
Method of Separating a Structure in a Semiconductor Device
Method for Packaging a Semiconductor Device
Plasma Treatment of a Semiconductor Surface for Enhanced Nucleation of a Metal-Containing Layer
Method and Program Product for Protecting Information in Eda Tool Design Views
Method of Making Exposed Pad Ball Grid Array Package
Oscillator Circuit with High Pass Filter and Low Pasds Filter in Output Stage
Surge Current Prevention Circuit and Dc Power Supply
Overcurrent Protection Circuit and Dc Power Supply
Back-Gated Semiconductor Device with a Storage Layer and Methods for Forming Thereof
Semiconductor Device Having Stressors and Method for Forming
Esd Protection for Passive Integrated Devices
Electronic Apparatus Interconnect Routing and Interconnect Routing Method for Minimizing Parasitic Resistance
Method of Forming a Semiconductor Device Having Dummy Features
Floating Gate Non-Volatile Memory and Method Thereof
Method for Determining Temperature Profile in Semiconductor Manufacturing Test
Transistor with Immersed Contacts and Methods of Forming Thereof
Volatile Corrosion Inhibitor Packages
Electrical Sensor for Real-Time Feedback Control of Plasma Nitridation
Method of Forming Device Having a Raised Extension Region
Thin-Film Capacitor with a Field Modification Layer and Methods for Forming the Same
Electronic Device Including a Fin-Type Transistor Structure and a Process for Forming the Electronic Device
Dual Plasma Treatment Barrier Film to Reduce Low-K Damage
Integrated Circuit Using Finfets and Having a Static Random Access Memory (Sram)
Ald Gate Electrode
Method of Packaging a Semiconductor Die and Package Thereof
Electronic Device Including a Static-Random-Access Memory Cell and a Process of Forming the Electronic Device
Electronic Device and Method for Operating a Memory Circuit
Memory and Method for Sensing Data in a Memory Using Complementary Sensing Scheme
System and Method for Control Logic Code Reordering Based on Stochastic Execution Time Information
Method for Producing Two Gates Controlling the Same Channel
Semiconductor Interconnect Having Adjacent Reservoir for Bonding and Method for Formation
Spacer T-Gate Structure for COSI2 Extendibility
Epi T-Gate Structure for COSI2 Extendibility
Method for Forming Multi-Layer Bumps on a Substrate
Method of Packaging Semiconductor Die Without Lead Frame or Substrate
Double-Gated Non-Volatile Memory and Methods for Forming Thereof
Method of Forming a Semiconductor Isolation Trench
System and Method for Reducing the Power Consumption of Clock Systems
Distributed Resource Access Protection
Mos Device with Multi-Layer Gate Stack
Mos Device with Nano-Crystal Gate Structure
Temperature Compensation Device and Method Thereof
Ground Shields for Semiconductors
Recessed Poly Extension T-Gate
Edge Seal for Improving Integrated Circuit Noise Isolation
Adaptive Variable Length Pulse Synchronizer
Method for Forming a Semiconductor-on-Insulator (Soi) Body-Contacted Device with a Portion of Drain Region Removed
Transistor with Reduced Gate-to-Source Capacitance and Method Therefor
Method to Selectively Form Regions Having Differing Properties and Structure
Methods and Apparatus for a High-Frequency Output Match Circuit
Embedded Substrate Interconnect for Underside Contact to Source and Drain Regions
Noise Isolation Between Circuit Blocks in an Integrated Circuit Chip
Cap Layer for an Aluminum Copper Bond Pad
Electronic Device and Method
Method for Improving Self-Aligned Silicide Extendibility with Spacer Recess Using an Aggregated Spacer Recess Etch (Asre) Integration
Method and Apparatus for Indicating Directionality in Integrated Circuit Manufacturing
Method and Apparatus for a Stepped-Drift Mosfet
Low Voltage Output Buffer and Method for Buffering Digital Output Data
Integrated Circuit with Functional State Configurable Memory and Method of Configuring Functional States of the Integrated Circuit Memory
Non-Volatile Memory Having a Multiple Block Erase Mode and Method Therefor
Method of Testing for Power and Ground Continuity of a Semiconductor Device
Method for Separately Optimizing Spacer Width for Two Transistor Groups Using a Recess Spacer Etch (Rse) Integration
Method for Separately Optimizing Spacer Width for Two or More Transistor Classes Using a Recess Spacer Integration
Methods and Apparatus for Thermal Isolation in Vertically-Integrated Semiconductor Devices
Composite Integrated Device and Methods for Forming Thereof
Enhanced Tone Detector Including Adaptive Multi-Bandpass Filter for Tone Detection and Enhancement
Electronic Device Testing System
Allocating Processing Resources for Multiple Instances of a Software Component
Charge Storage Structure Formation in Transistor with Vertical Channel Region
Clock Generation Circuit
Method for Forming Reinforced Interconnects on a Substrate
Dynamic Timing Adjustment in a Circuit Device
Warp Compensated Package and Method
Frozen Material Detection Using Electric Field Sensor
Semiconductor Device with a Protected Active Die Region and Method Therefor
Process for Forming an Electronic Device Including Semiconductor Layers Having Different Stresses
Silicon Deposition Over Dual Surface Orientation Substrates to Promote Uniform Polishing
Process of Forming an Electronic Device Including a Semiconductor Island Over an Insulating Layer
Process of Forming an Electronic Device Including a Semiconductor Fin
Electrical Field Sensors for Detecting Fluid Presence or Level
Selective Uniaxial Stress Relaxation by Layout Optimization in Strained Silicon on Insulator Integrated Circuit
Integrated Circuit Encapsulation and Method Therefor
Method and Apparatus for Forming an Electrical Connection to a Semiconductor Substrate
Non-Volatile Memory Wih Controlled Program/Erase
Data processor having dynamic control of instruction prefetch buffer depth and method therefor
Non-Overlapping Multi-Stage Clock Generator System
Phase Detector Device and Method Thereof
Slew Rate Control of a Charge Pump
Circuit and Method for Latch Bypass
Polishing Pad, a Polishing Apparatus, and a Process for Using the Polishing Pad
Polishing Pad, a Polishing Apparatus, and a Process for Using the Polishing Pad
Patent:
7,179,151 →
Application:
11/390,292 →
Semiconductor Device and Method for Forming the Same
Error Correction Device and Methods Thereof
Method of Making a Multiple Crystal Orientation Semiconductor Device
Methods and Apparatus for a Reduced Inductance Wirebond Array
Composite Capacitor and Method for Forming the Same
Lead Frame Based, Over-Molded Semiconductor Package with Integrated Through Hole Technology (Tht) Heat Spreader Pin(S) and Associated Method of Manufacturing
Electric Field Reciprocal Displacement Sensors
Programmable Cell
Methods and Apparatus for a Mems Varactor
Patent:
7,141,989 →
Application:
11/401,592 →
Integrated Circuit with Different Channel Materials for P and N Channel Transistors and Method Therefor
Trimming Circuit and Electronic Circuit
Transistor and Method with Dual Layer Passivation
Stressor Integration and Method Thereof
Process of Forming an Electronic Device Including a Layer Formed Using an Inductively Coupled Plasma
Selective Bit Error Detection at a Bus Device
Non-Volatile Memory Cell
Processor and Method for Altering Address Translation
Broadcast Handoff Between Communication Networks
Method of Forming Stackable Package
Reference Circuit and Method for Generating a Reference Signal from a Reference Circuit
Electronic Device Including Semiconductor Fins and a Process for Forming the Electronic Device
Multi-Level Voltage Adjustment
Method of Stimulating Die Circuitry and Structure Therefor
Engineering Strain in Thick Strained-Soi Substrates
Method for Forming a Semiconductor Structure Having a Strained Silicon Layer
Low Voltage Circuit with Variable Substrate Bias
Heatsink Moldlocks
Process of Forming Electronic Device Including a Densified Nitride Layer Adjacent to an Opening Within a Semiconductor Layer
Delay configurable device and methods thereof
Hardware Monitor of Lin Time Budget
Contention-Free Hierarchical Bit Line in Embedded Memory and Method Thereof
Model Correspondence Method and Device
System and Method for Reducing Current in a Device During Testing
Patent:
7,218,119 →
Application:
11/444,087 →
Die Level Metal Density Gradient for Improved Flip Chip Package Reliability
Patent:
7,276,435 →
Application:
11/445,657 →
System and Method for Polar Modulation Using Power Amplifier Bias Control
In-Circuit Vt Distribution Bit Counter for Non-Volatile Memory Devices
Dynamically Changing Media Compression Format in Compressed Domain
Patent:
8,102,916 →
Application:
11/448,447 →
Methods and Apparatus for a Semiconductor Device Package with Improved Thermal Performance
Methods and Apparatus for Thermal Management in a Multi-Layer Embedded Chip Structure
Low Pin Count Reset Configuration
Microelectronic Assembly with Back Side Metallization and Method for Forming the Same
A Direct Digital Synthesis Circuit
Coil-Less Overtone Crystal Oscillator
Data Latch with Minimal Setup Time and Launch Delay
Voltage Control Circuit Having a Power Switch
Current Comparison Based Voltage Bias Generator for Electronic Data Storage Devices
Bus Having a Dynamic Timing Bridge
Oscillator with Stacked Amplifier
Double-Rate Memory
Power De-Rating Reduction in a Transmitter
Overtone Crystal Oscillator Automatic Calibration System
Method of Forming Crack Arrest Features in Embedded Device Build-Up Package and Package Thereof
Method and System for Reducing Delay Noise in an Integrated Circuit
Stacked Loop Antenna
System and Method for Evm Self-Test
Manipulation of media streams in the compressed domain
Patent:
8,582,650 →
Application:
11/486,190 →
Concurrent Programming and Program Verification of Floating Gate Transistor
Pvt Variation Detection and Compensation Circuit
Method for Testing Integrated Circuit, and Wafer
Apparatus for Current Sensing
Temperature Sensor Device and Methods Thereof
Semiconductor Integrated Circuit
Discharge Device and Dc Power Supply System
Deglitch Circuit
Power Supply Circuit
Coherent Access Register Data Transfer Device and Methods Thereof
Multiple Sensor Thermal Management for Electronic Devices
Methods and Apparatus for Simulating Distributed Effects
Method for Fabricating Dual-Metal Gate Device
Input Circuit for Receiving a Variable Voltage Input Signal and Method
Feedback Reduction for Mimo Precoded System by Exploiting Channel Correlation
Sequence-Independent Power-on Reset for Multi-Voltage Circuits
Digital Clock Frequency Multiplier
User Equipment Frequency Allocation Methods and Apparatus
Trimming Circuit, Electronic Circuit, and Trimming Control System
Signal Detection Device and Methods Thereof
System and Method for Memory Array Access with Fast Address Decoder
Method for Damage Avoidance in Transferring an Ultra-Thin Layer of Crystalline Material with High Crystalline Quality
Method for Maintaining Topographical Uniformity of a Semiconductor Memory Array
Ripple Filter Circuit
Method and Apparatus for Designing Semiconductor Integrated Circuit
Latching Input Buffer Circuit with Variable Hysteresis
Streamlined Transcoder Architecture
Patent:
8,311,114 →
Application:
11/567,678 →
Leadframe for a Semiconductor Device
Method and Device to Wake-Up Nodes in a Serial Data Bus
Wireless Mobile Device
Semiconductor Switch Arrangement and an Electronic Device
Virtual Address Cache and Method for Sharing Data Using a Unique Task Identifier
Power Semiconductor Device
A Design Rule Checking System and Method, for Checking Compliance of an Integreated Circuit Design with a Plurality of Design Rules
Descriptor-Based Memory Management Unit and Method for Memory Management
Power Switching Apparatus with Open-Load Detection
Power Switching Apparatus with Overload Protection
Method of Forming a Semiconductor Package and Structure Thereof
Reference Circuit
Varactor
Level Realignment Following an Epitaxy Step
Integrated Matching Network and Method for Manufacturing Integrated Matching Networks
System and Method for Reducing Edge Effect
Variable Resurf Semiconductor Device and Method
System and Method of Determining Deblocking Control Flag of Scalable Video System for Indicating Presentation of Deblocking Parameters for Multiple Layers
Cell Phone Device
Communication Steering for Use in a Multi-Master Shared Resource System
Architecture for Combining Media Processing with Networking
Patent:
7,830,800 →
Application:
11/611,356 →
Method and System for Transmitting Data
Patent:
7,378,993 →
Application:
11/619,932 →
Light Erasable Memory and Method Therefor
Reduction of Block Effects in Spatially Re-Sampled Image Information for Block-Based Image Coding
Digital Clock Generating Circuit and Method of Operation
Handheld Device for Dialing of Phone Numbers Extracted from a Voicemail
Method and Apparatus for Affecting a Portion of an Integrated Circuit
Programming and Erasing Structure for a Floating Gate Memory Cell and Method of Making
Electronic Device Including Trenches and Discontinuous Storage Elements
Process of Forming an Electronic Device Including Fins and Discontinuous Storage Elements
Electronic Device Including Trenches and Discontinuous Storage Elements and Processes of Forming and Using the Same
Method and Apparatus for Closed Loop Offset Cancellation
System and Method for Reducing Noise in Sensors with Capacitive Pickup
Method of Making a Semiconductor Device Having High Voltage Transistors, Non-Volatile Memory Transistors, and Logic Transistors
Methods and Apparatus for a Multi-Mode Analog-to-Digital Converter
Reducing a Peak-to-Average Ratio of a Signal Using Filtering
Reducing a Peak-to-Average Ratio of a Signal
Method of Forming a Multi-Bit Nonvolatile Memory Device
Split Gate Memory Cell Method
Localized Alloying for Improved Bond Reliability
Video De-Interlacer Using Motion Residue Compensation
Secure Data Access Methods and Apparatus
Single Stage Cyclic Analog to Digital Converter with Variable Resolution
Adaptive Threshold Wafer Testing Device and Method Thereof
Successive Interference Cancellation Based on the Number of Retransmissions
Temperature Based Dram Refresh
High Voltage Field Effect Device and Method
High Voltage Protection for a Thin Oxide Cmos Device
Load Independent Voltage Regulator
Method and Device for Programming Anti-Fuses
Systems, Apparatus and Method for Performing Digital Pre-Distortion Based on Lookup Table Gain Values
Video De-Interlacer Using Pixel Trajectory
Apparatus and Method for Controlling Voltage and Frequency Using Multiple Reference Circuits
Integrated Circuit and a Method for Secure Testing
Integrated Circuit and a Method for Testing a Multi-Tap Integrated Circuit
Method and System for Improving the Manufacturability of Integrated Circuits
Broadcasting of Textual and Multimedia Information
System and Method for Reducing Current in a Device During Testing
Memory with Serial Input-Output Terminals for Address and Data and Method Therefor
Method and System for Incorporating via Redundancy in Timing Analysis
Current Sensor Device
Integrated Circuit with a Programmable Delay and a Method Thereof
Method of Blocking a Void During Contact Formation
Circuit and Method for Generating Fixed Point Vector Dot Product and Matrix Vector Values
Apparatus for Optimizing Diode Conduction Time During a Deadtime Interval
Method and Apparatus for Providing Structural Support for Interconnect Pad While Allowing Signal Conductance
Method and System for Simultaneous Reads of Multiple Arrays
Integrated Circuit with Continuous Testing of Repetitive Functional Blocks
Systems, Apparatus, and Methods for Performing Digital Pre-Distortion with Feedback Signal Adjustment
Recording Device Capable of Determining the Media Type Based on Detecting the Capacitance of Pair Electrodes.
Method and Device for Designing Semiconductor Integrated Circuit
Programmable Bias for a Memory Array
System and Method for Operating a Communications System
Current-Mode Memory Cell
Method of Coating a Surface with Nanoparticles
Device Having Failure Recovery Capabilities and a Method for Failure Recovery
Lead-Frame Circuit Package
Control Apparatus and Method of Regulating Power
Techniques for Detecting Open Integrated Circuit Pins
Speedpath Repair in an Integrated Circuit
Method for Manufacturing a Passive Integrated Matching Network for Power Amplifiers
Electronic Device Including a Memory Array and Conductive Lines
Mode Transitioning in a Dc/Dc Converter Using a Constant Duty Cycle Difference
Method and System of Executing a Software Application in Highly Constrained Memory Situation
Flip-Flop Having Logic State Retention During a Power Down Mode and Method Therefor
Rf Circuit with Control Unit to Reduce Signal Power Under Appropriate Conditions
Fast Predictive Automatic Gain Control for Dynamic Range Reduction in Wireless Communication Receiver
System and Method for Monitoring Clock Signal in an Integrated Circuit
Miller Capacitance Tolerant Buffer Element
System and Method for Reducing Power Consumption in a Low-Density Parity-Check (Ldpc) Decoder
Efficient Transcoding Between Formats Using Macroblock Buffer
Patent:
8,179,964 →
Application:
11/851,879 →
Architecture for Multiple Graphics Planes
Patent:
8,698,838 →
Application:
11/851,912 →
Graphics Overlay System for Multiple Displays Using Compressed Video
Patent:
8,483,389 →
Application:
11/851,924 →
Method for Conversion Between Yuv 4:4:4 and Yuv 4:2:0
Patent:
8,139,081 →
Application:
11/851,933 →
Perceptually Adaptive Quantization Parameter Selection
Patent:
8,064,517 →
Application:
11/852,199 →
Voltage Regulator and Method for Providing a Regulated Output
Patent:
7,423,416 →
Application:
11/853,939 →
Latch Device Having Low-Power Data Retention
System and Method for Testing Memory Blocks in an Soc Design
Bus Interconnect with Flow Control
Method and Apparatus for Mobility Enhancement in a Semiconductor Device
Sdram Sharing Using a Control Surrogate
Storage Circuit and Method Therefor
Clock Circuit with Clock Transfer Capability and Method
Crystal Oscillator Circuit Having Fast Start-Up and Method Therefor
Touch Panel Detection Circuitry and Method of Operation
Method for Race Prevention and a Device Having Race Prevention Capabilities
Charge Pump and Control Scheme
System and Method for Reducing Power Consumption of a Transistor-Based Circuit Having Multiple Operational Modes Characterized by Different Power Consumption Level
Voltage Converter Apparatus and Method Therefor
Electronic Switch Circuit, Converter and Method of Operation
Current Driver Circuit and Method of Operation Therefor
Current Driver Circuit and Method of Operation Therefor
Adaptive Protection Circuit for a Power Amplifier
Apparatus for Cleaning of Circuit Substrates
Integrated Circuit and a Method for Designing a Boundary Scan Super-Cell
Method of Distancing a Bubble and Bubble Displacement Apparatus
Method and Device for High Speed Testing of an Integrated Circuit
Cleaning Solution for a Semiconductor Wafer
Method and Device for Processing Image Data Stored in a Frame Buffer
Treatment Solution and Method of Applying a Passivating Layer
Hybrid Method and Device for Transmitting Packets
Device and Method for Media Access Control
Method and Device for Frame Synchronization
Twisted Pair Communication System, Apparatus and Method Thereof
Electronic Device Comprising a Gate Electrode Including a Metal-Containing Layer Having One or More Impurities
Circuit for Providing an Approximately Constant Resistance and/or Current and Method Therefor
Knock Signal Detection in Automotive Systems
Bypassable Low Noise Amplifier Topology with Multi-Tap Transformer
Dual Sensor System Having Fault Detection Capability
Method for Protecting a Security Real Time Clock Generator and a Device Having Protection Capabilities
Patent:
7,733,117 →
Application:
11/942,799 →
Error Detector in a Cache Memory Using Configurable Way Redundancy
Short Circuit and Over-Voltage Protection for a Data Bus
Method and Controller for Detecting a Stall Condition in a Stepping Motor During Micro-Stepping
Sensor Device and Method Thereof
Electronic Device Operable to Protect a Power Transistor When Used in Conjunction with a Transformer
Liquid Level Sensing Device and Method
Esd Protection for Passive Integrated Devices
Remotely Modifying Data in Memory in a Mobile Device
Device and Method for Securing Software
Method of Forming a Semiconductor Structure
Encryption Apparatus and Method Therefor
Device and Method for Arbitrating Between Direct Memory Access Task Requests
Device and Method for Compensating for Voltage Drops
Compensation for Parasitic Coupling Between Rf or Microwave Transistors in the Same Package
Method of Forming a Continuous Layer of a First Metal Selectively on a Second Metal and an Integrated Circuit Formed from the Method
Temperature Sensing Device
Voltage Regulator with Pass Transistors Carrying Different Ratios of the Total Load Current and Method of Operation Therefor
Switch Arrangement, Integrated Circuit, Activation System
Microphone Amplification Arrangement and Integrated Circuit Therefor
Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device
Method and System for Estimating Power Consumption of Integrated Circuit Design
Tuning a Second Order Intercept Point of a Mixer in a Receiver
Battery-Less Electronic Device
Embedded Substrate Interconnect for Underside Contact to Source and Drain Regions
Circuit Having Logic State Retention During Power-Down and Method Therefor
Self Regulating Biasing Circuit
System and Method for Preventing a Race Condition
Patent:
7,962,805 →
Application:
12/026,595 →
Configurable Receiver and a Method for Configuring a Receiver
Patent:
7,978,757 →
Application:
12/028,018 →
Shielded Integrated Circuit Pad Structure
Peripheral Module Register Access Methods and Apparatus
Packaged Integrated Circuit with Enhanced Thermal Dissipation
Data Processor Device Having Trace Capabilities and Method
Data Processing Device and Method of Halting Exception Processing
Circuit Device with at Least Partial Packaging and Method for Forming
Method of Low Power Pll for Low Jitter Demanding Applications
Patent:
7,786,809 →
Application:
12/041,687 →
Automatic Calibration Lock Loop Circuit and Method Having Improved Lock Time
Lock Loop Circuit and Method Having Improved Lock Time
System and Method for Reducing Power Consumption of Memory in an I/O Controller
Intra Frame Beating Effect Reduction
Patent:
8,654,844 →
Application:
12/049,238 →
Zero Input Current-Drain Comparator with High Accuracy Trip Point Above Supply Voltage
Led Driver with Dynamic Power Management
Quarter Duty Cycle Pulse Generator for Interleaved Switching Mixer
Hardware Managed Context Sensitive Interrupt Priority Level Control
Hybrid Transistor Based Power Gating Switch Circuit and Method
Pore Sealing and Cleaning Porous Low Dielectric Constant Structures
Loop Gain Equalizer for Rf Power Amplifier
Field-Effect Semiconductor Device and Method of Forming the Same
Gate Electrode Silicidation Process
Method and a Computer Readable Medium for Performing Static Timing Analysis of a Design of an Integrated Circuit
Receiver and a Method for Channel Estimation
Interconnect and a Method for Designing an Interconnect
Power Saving in Signal Processing in Receivers
Spin-Dependent Tunnelling Cell and Method of Formation Thereof
Integrated Circuit and a Method for Selecting a Voltage in an Integrated Circuit
Receiver Configurable in a Plurality of Modes
System and Method for Cleaning a Conditioning Device
Method for Cleaning a Semiconductor Structure and Chemistry Thereof
Electronic Device and Method for Controlling Current of a Processor Load by Slewing Clock Frequency
System and Method for Controlling Voltage Level and Clock Frequency Supplied to a System
Method for Testing a Slurry Used to Form a Semiconductor Device
Method for Forming a Semiconductor Device Using Optical Proximity Correction for the Optical Lithography
Device and Method for Configuring Input/Output Pads
Method and System for Clock Skew Reduction in Clock Trees
Method for Managing Under-Run and a Device Having Under-Run Management Capabilities
System and Method for Removing Particles from a Polishing Pad
Device and Method for Compensating for Voltage Drops
Multi-Port High-Level Cache Unit and a Method for Retrieving Information from a Multi-Port High-Level Cache Unit
Method and Device for Managing Multi-Frames
Method for Processing Atm Cells and a Device Having Atm Cell Processing Capabilities
Wireless Subscriber Communication Unit and Method of Power Control with Back-Off Thererfore
Method and System for Compensating for the Effect of Phase Drift in a Data Sampling Clock
Power Converter with Improved Efficiency
Leadframe for Packaged Electronic Device with Enhanced Mold Locking Capability
Laterally Grown Nanotubes and Method of Formation
Spring Member for Use in a Microelectromechanical Systems Sensor
Resonant Accelerometer with Low Sensitivity to Package Stress
Vehicular Seatbelt Restraint with Selectively Disabled Inertia Reel Assembly
Drive Arrangement for Activating a Car Safety Device Activation Element
Temperature Compensation Circuit, Trimming Circuit, and Acceleration Detector
Virtual Direct Memory Access (Dma) Channel Technique with Multiple Engines for Dma Controller
Semiconductor Devices
Differential Current Sensor Device and Method
Testing of Multiple Integrated Circuits
Multiple Core System
Process of Forming an Electronic Device Including a Resistor-Capacitor Filter
Smart/Active RFID Tag for Use in a WPAN
Techniques for Performing Discrete Fourier Transforms on Radix-2 Platforms
System and Method for Establishing a Wpan with Precise Locationing Capability
Voltage Reference Device and Methods Thereof
Control and Data Information Communication in a Wireless System
Low Dropout Voltage Regulator Using Multi-Gate Transistors
Touch Screen Detection and Diagnostics
Test Interposer Having Active Circuit Component and Method Therefor
Amplifier Circuit Having Dynamically Biased Configuration
Error Correcting Viterbi Decoder
Immersion Lithography Apparatus and Method of Performing Immersion Lithography
Improvements in or Relating to Lead Frame Based Semiconductor Package and a Method of Manufacturing the Same
Device and Method for Evaluating Electrostatic Discharge Protection Capabilities
Controlling the Access of Master Elements to Slave Elements Over a Communication Bus
Regulated Voltage System and Method of Protection Therefor
Method and Apparatus for Conditioning a Cmp Pad
Device and a Method for Estimating Transistor Parameter Variations
Method for Protecting a Secured Real Time Clock Module and a Device Having Protection Capabilities
Device Having Clock Generating Capabilities and a Method for Generating a Clock Signal
Techniques for Reducing Joint Detection Complexity in a Channel-Coded Multiple-Input Multiple-Output Communication System
Spool Braking Device for Fishing Reel
Electronic Device Including a Semiconductor Fin
System and Method for Arbitrating Between Memory Access Requests
Method for Generating a Output Clock Signal Having a Output Cycle and a Device Having a Clock Signal Generating Capabilities
Electronic Device Including a Transistor Structure Having an Active Region Adjacent to a Stressor Layer
Stacked Cascode Current Source
Led Driver with Frame-Based Dynamic Power Management
Method of Providing a Data Signal for Channel Estimation and Circuit Thereof
Reconfigurable Multi-Processing Coarse-Grain Array
Fourier Transform Processing and Twiddle Factor Generation
Error Correcting Viterbi Decoder
Method for Transferring a Predetermined Pattern Reducing Proximity Effects
Method of Forming a Semiconductor Package Including Two Devices
Dual-Loop Dc-to-Dc Converter Apparatus
Process of Using a Polishing Apparatus Including a Platen Window and a Polishing Pad
Semiconductor Fabrication Process Including Silicide Stringer Removal Processing
Multiple Device Types Including an Inverted-T Channel Transistor and Method Therefor
Electronic Device Having a Memory Element and Method of Operation Therefor
Acceleration Sensor Arrangement, Safing Arrangement for an Activation System, Activation System
Lin Bus Network, Integrated Circuit and Method of Communicating Thereon
Device and Method for Testing a Noise Immunity Characteristic of Analog Circuits
Method for Scheduling Atm Cells and a Device Having Atm Cell Scheduling Capabilities
Method of Patterning a Layer Using a Pellicle
Software Pipelining
Testing Non-Volatile Memory Devices for Charge Leakage
Device and Method for Testing a Device
Semiconductor Device Structure and Integrated Circuit Therefor
Method and Device for Processing Frames
Method and Device for Recognizing a Synchronization Message from a Wireless Telecommunication Device
Method and Apparatus for Enhanced Data Rate Adaptation and Lower Power Control in a Wlan Semiconductor Chip
Method and System for Tuning an Antenna
Bitline Current Generator for a Non-Volatile Memory Array and a Non-Volatile Memory Array
Non-Volatile Memory Device and a Programmable Voltage Reference for a Non-Volatile Memory Device
Wordline Driver for a Non-Volatile Memory Device, a Non-Volatile Memory Device and Method
Methods and apparatus for reordering data
Electronic Device and Integrated Circuit Comprising a Delta-Sigma Converter and Method Therefor
Apparatus for Detecting Clock Failure and Method Therefor
Process for Filling Recessed Features in a Dielectric Substrate
Bias Circuit for a Radio Frequency Power-Amplifier and Method Therefor
Method for Driving a Ptc Electrical Load Element
Lin Network, Integrated Circuit and Method Therefor
Amplifier Circuit and Integrated Circuit Therefor
Sin-Cos Sensor Arrangement, Integrated Circuit and Method Therefor
Method and System for Signal Error Determination and Correction in a Flexray Communication System
Device and Method for Handling Metastable Signals
Method for Transmitting a Datum from a Time-Dependent Data Storage Means
Voltage Regulation Apparatus and Method of Varying a Number of Current Sources to Provide a Regulated Voltage
Method and Device for Power Management
Microprocessor and Method for Register Addressing Therein
Transmitting Device and Method of Tuning the Transmitting Device
Method for Gamma Correction and a Device Having Gamma Correction Capabilities
Method and System for Grouping Interrupts from a Time-Dependent Data Storage System
Method and Apparatus for Transmitting Data in a Flexray Node
Self-Aligning Resonator Filter Circuits
Mos Devices with Multi-Layer Gate Stack
Intermediate Compression of Reference Frames for Transcoding
Tunable Antifuse Elements
Media Transmission Using Aggregated Bandwidth of Disparate Communication Channels
Patent:
8,050,289 →
Application:
12/362,389 →
Motion Estimation Engine for Performing Multiple Types of Operations
Patent:
8,503,533 →
Application:
12/362,394 →
Enhanced Deinterlacing Using Predictors from Motion Estimation Engine
Patent:
8,508,661 →
Application:
12/362,415 →
Providing Trick Mode for Video Stream Transmitted Over Network
Patent:
8,265,168 →
Application:
12/362,423 →
Motion Compensated Noise Reduction Using Shared Motion Estimation Engine
Patent:
8,351,510 →
Application:
12/362,436 →
Architecture for Adjusting Bit Rate Based on Measured Quality
Patent:
8,743,954 →
Application:
12/362,453 →
Switched-Capacitor Circuits, Integration Systems, and Methods of Operation Thereof
Led Driver with Dynamic Headroom Control
Linear Voltage Controlled Variable Attenuator with Linear Db/V Gain Slope
Method for Processing Cdma Signals and a Device Having Cdma Signal Capabilities
Memory Management Unit and Method of Accessing an Address
Method and Apparatus for Improvements in Chip Manufacture and Design
Device and Method for Power Management
Device Having Priority Upgrade Mechanism Capabilities and a Method for Updating Priorities
Protection Circuit Apparatus
Integrated Matching Networks and Rf Devices That Include an Integrated Matching Network
Clock Tree Adjustable Buffer
Patent:
7,917,875 →
Application:
12/390,858 →
Virtual Ground Memory Array and Method Therefor
Huffman Search Algorithm for Aac Decoder
Patent:
7,773,003 →
Application:
12/398,189 →
Antifuse Elements
Vco Control and Methods Therefor
Thin-Film Capacitor with a Field Modification Layer
Mobile Communications Device, Controller, and Method for Controlling a Mobile Communications Device
Improvements in or Relating to Headsets
Analogue-To-Digital Converter Apparatus and Method of Reusing an Analogue-to-Digital Converter Circuit
Led Driver with Dynamic Power Management
Capacitive Sensors Including Gain and Active-Filtered Sampling Stages
Network and Method for Setting a Time-Base of a Node in the Network
Data Communication System and Method
Memory System with Ecc-Unit and Further Processing Arrangement
Transmission and Reception Channel Selection for Communicating Between a Transmitter Unit and a Receiver Unit
Test Unit for Testing the Frequency Characteristic of a Transmitter
Power Supply Switching Apparatus with Severe Overload Detection
Wireless Communication Device, Integrated Circuit and Method of Timing Synchronisation
Electronic Device, Integrated Circuit and Method Therefor
Communication Device, Integrated Circuit and Method Therefor
Electronic Device, Integrated Circuit and Method for Selecting of an Optimal Sampling Clock Phase
Very Low Intermediate Frequency (Vlif) Receiver
Calibration Signal Generator
Device and Method for Testing a Circuit
Measurement of Critical Dimensions of Semiconductor Wafers
Data Communication Unit, Data Communication Network and Method of Decoding
Method of Optimising the Rank of a Mmse Channel Equaliser
Method and Apparatus for Converting Signals
Wireless Communication Unit, Integrated Circuit Comprising a Voltage Controlled Oscillator and Method of Operation Therefor
Analogue to Digital Converters
Anticipation of Power on of a Mobile Device
Method and Apparatus to Receive Location Information in a Diversity Enabled Receiver
Macroblock Based Scaling of Images Using Reduced Memory Bandwidth
Patent:
8,872,856 →
Application:
12/534,758 →
Cascading Multiple Video Transcoders in a Video Processing System
Patent:
8,767,838 →
Application:
12/553,228 →
Standby Control Circuit and Method
Stackable Molded Packages and Methods of Making the Same
Optimized Motion Compensation and Motion Estimation for Video Coding
Patent:
8,411,749 →
Application:
12/572,151 →
Plasma Treatment of a Semiconductor Surface for Enhanced Nucleation of a Metal-Containing Layer
Integrated Circuit Comprising Error Correction Logic, and a Method of Error Correction
Device and Method for Sharing Charge
Relating to Diagnostics of a Capacitive Sensor
Data Processing Control Unit for Controlling Multiple Data Processing Operations
Device and Method for State Retention Power Gating
Circuit, Integrated Circuit and Method for Dissipating Heat from an Inductive Load
Unified Memory Architecture and Display Controller to Prevent Data Feed Under-Run
Semiconductor Wafer Processing
Integrated Circuit, Electronic Device and Esd Protection Therefor
Power Supply Controller for Multiple Lighting Components
Diagnosis for Mixed Signal Device for Use in a Distributed System
Video Processing System, Integrated Circuit, System for Displaying Video, System for Generating Video, Method for Configuring a Video Processing System, and Computer Program Product
Digital Squib Driver Circuit
System and Method for Secure Real Time Clocks
Data Processing System, Data Processing Method, and Apparatus
Wireless Communication Unit, Baseband Module, Radio Frequency Module, Wireless Terminal and Computer Program Product
Data Processing System, Method for Processing Data and Computer Program Product
Integrated Circuit, Wireless Communication Unit and Method for Determining Quadrature Imbalance
Device and Method for Transmitting Data in a Wideband Wireless Network and Computer Program Product
Method of Fast Tracking and Jitter Improvement in Asynchronous Sample Rate Conversion
Integrated Circuit Encapsulation and Method Therefor
Method and Apparatus for Indicating Directionality in Integrated Circuit Manufacturing
Electronic Apparatus Interconnect Routing
Electronic Device Including Trenches and Discontinuous Storage Elements
Circuits and Methods for Buffering and Communicating Data Signals
Dynamic Voltage Scaling Interface
Circuit Arrangement for Filtering Unwanted Signals from a Clock Signal, Processing System and Method of Filtering Unwanted Signals from a Clock Signal
Start-Up Circuit Element for a Controlled Electrical Supply
Method and Decoder for Decoding a Wireless Transmission from a Predefined User
Wireless Communication Unit, Integrated Circuit and Method of Power Control Therein
Voltage Supply Circuitry and Integrated Circuit Therefor
Motor Controller for Determining a Position of a Rotor of an Ac Motor, Ac Motor System, and Method of Determining a Position of a Rotor of an Ac Motor
Band-Gap Voltage Reference Circuit Having Multiple Branches
Timer Unit, System, Computer Program Product and Method for Testing a Logic Circuit
Microprocessor, System for Controlling a Device and Apparatus
Power Management Arrangement for a Mobile Device
Method and System of Adaptive Predistortion of a Wireless Transmitter
Prolonging Internal Power Supply Life in a Mobile Communication Device
High Voltage Protection for a Thin Oxide Cmos Device
Generation, Injection and Use of Pilot Tones for Gyro System Characterization
Transistor Devices with Nano-Crystal Gate Structures
Overcurrent Protection Circuit, Integrated Circuit, Apparatus and Computer Program Product
System and Method to Improve Switching in Power Switching Applications
Amplifier Circuit Audio Circuit and Electronic Device
Semiconductor Device and Apparatus Including Semiconductor Device
Semiconductor Device and Apparatus Including Semiconductor Device
Amplifier Circuit, Electronic Device, Method for Configuring an Amplifier Circuit
Process for Forming an Electronic Device Including a Fin-Type Transistor Structure
Data Transfer Coherency Device and Methods Thereof
Integrated Circuit Using Finfets and Having a Static Random Access Memory (Sram)
Memory Mapping System, Request Controller, Multi-Processing Arrangement, Central Interrupt Request Controller, Apparatus, Method for Controlling Memory Access and Computer Program Product
Performance estimation for adjusting processor parameter to execute a task taking account of resource available task inactive period
Semiconductor Device and Differential Amplifier Circuit Therefor
Processor Based System Having Ecc Based Check and Access Validation Information Means
Method and Apparatus for Regulating a Field Current for an Alternator Device
Lead Frame Based, Over-Molded Semiconductor Package with Integrated Through Hole Technology (Tht) Heat Spreader Pin(S) and Associated Method of Manufacturing
Voltage Regulator with an Emitter Follower Differential Amplifier
MEMORY MANAGEMENT and method for allocation using free-list
Method and Apparatus for Decoding Received Data Signals
Sigma-Delta Modulator Apparatus and Method of Generating a Modulated Output Signal
Analog to Digital Converter with Amplifier
Processor for Use as a Path Searcher of a Spread Spectrum Receiver and a Method of Operation of the Processor
Architecture For Combining Media Processing With Networking
Patent:
8,619,570 →
Application:
12/898,591 →
Dc Compensation for Vlif Signals
Method for Protecting a Cryptographic Module and a Device Having Cryptographic Module Protection Capabilities
Apparatus and a Method for Detecting Faults in the Delivery of Electrical Power to Electrical Loads
Clock Signal Generating Arrangement for a Communication Device
Poly-Resistor, and Linear Amplifier
Microprocessor Having a Low-Power Mode and a Non-Low Power Mode, Data Processing System and Computer Program Product
Microcontroller Device, Microcontroller Debugging Device, Method of Debugging a Microcontroller Device, Microcontroller Kit
Pll System and Method for Controlling a Gain of a Vco Circuit
Multiplexing and Demultiplexing Data
Synchronization of Stateful Elements in a Processing Resource Using a Scan Chain
Multiple Sensor Thermal Management for Electronic Devices
Method for Sampling Data and Apparatus Therefor
Display Controller, Image Processing System, Display System, Apparatus and Computer Program Product
Electrostatic Discharge Protection Circuit, Equipment and Method
System for Dynamically Distributing an Available Memory Resource to Redundant and Non-Redundant Storage Areas Using Ram Routing Logic
Semiconductor Device and Method of Electrostatic Discharge Protection Therefor
Method and Apparatus for Generating a Modulated Waveform Signal
Processing Position-Related Input Data from a Rotational Machine Whose Angular Speed Is Variable
Die Temperature Estimator
Computational Generation of Narrow-Bandwidth Digital Signals
Wake-Up Control System and Method for Controlling Receiver Wake-Up
Transistors with Immersed Contacts
Wireless Communication Unit, Integrated Circuit and Method of Power Control of a Power Amplifier Therefor
Method and Apparatus for Handling an Output Mismatch
Bus Driver for Avoiding an Overvoltage
Semiconductor Device and Electronic Device
Allocation of Communication Channels
Operating Parameter Control for a Power Amplifier
Dual-Pipeline Cabac Encoder Architecture
Patent:
8,798,139 →
Application:
13/172,773 →
Context Model Cache-Management in a Dual-Pipeline Cabac Architecture
Patent:
9,258,565 →
Application:
13/172,775 →
Lead Frame Based Semiconductor Package and a Method of Manufacturing the Same
Process of Forming an Electronic Device Including a Resistor-Capacitor Filter
Media Transmission Using Aggregated Bandwidth of Disparate Communication Channels
Patent:
8,526,465 →
Application:
13/227,340 →
Memory and Method for Sensing Data in a Memory Using Complementary Sensing Scheme
Child Car Seat for a Land Vehicle
Unified Scaling with Differential Coding for Internal Bit Depth Extension and Reference Frame Compression
Patent:
8,923,389 →
Application:
13/348,774 →
Localized Alloying for Improved Bond Reliability
Method for Driving a Ptc Electrical Load Element
Method of Forming a Semiconductor Structure
Efficient Transcoding Between Formats Using Macroblock Buffer
Patent:
8,588,300 →
Application:
13/450,307 →
Transistors with Dual Layer Passivation
Dynamic Logic Circuit
Patent:
8,487,657 →
Application:
13/484,870 →
Streamlined Transcoder Architecture
Patent:
8,488,679 →
Application:
13/610,522 →
Transistors with Immersed Contacts
Motion Adaptive Deinterlacer
Patent:
8,704,945 →
Application:
13/618,536 →
Optimized Motion Compensation and Motion Estimation for Video Coding
Noise Isolation Between Circuit Blocks in an Integrated Circuit Chip
Processing a Video Stream in Real Time Based on Binary Information of the Video Stream
Graphics Overlay System for Multiple Displays Using Compressed Video
Patent:
9,161,030 →
Application:
13/900,027 →
Multiplexing and Demultiplexing Data
Apparatus and a Method for Detecting Faults in the Delivery of Electrical Power to Electrical Loads
Architecture for Multiple Graphics Planes
Patent:
9,053,752 →
Application:
14/188,642 →
Enhanced Digital Video Recording Using Video Transcoding
Patent:
9,350,968 →
Application:
14/296,228 →
Power Management for a Battery-Powered Handheld Audio Device
Warp Compensated Electronic Assemblies
Device and Method for Compensating for Voltage Drops
Memory Management and Method for Allocation Using Free-List
Low Pressure, 2 Step Nucleation, Tungsten Chemical Vapor Deposition Process for Achieving Superior via Fill in Sub 0.25UM Integrated Circuit Applications
Application:
60/152,407 →
Rio Bus Protocol
Application:
60/175,856 →
Motion sensing techniques and analysis for direct tire pressure monitoring
Application:
60/419,487 →
Using InGaP pHEMT for power amplifier operation over temperature under digital modulation
Application:
60/523,341 →
Integrated configurable fault detector circuit
Application:
60/619,155 →
Manipulation of media streams in the compressed domain
Application:
60/758,776 →
Compressing Reference Frames
Application:
61/025,526 →
Architecture For Adjusting Bit Rate Based On Measured Quality
Application:
61/025,530 →
Media Transmission Using Aggregated Bandwidth of Disparate Communication Channels
Application:
61/025,609 →
Enhanced Deinterlacing and Noise Reduction Using Predictors from Motion Estimation Engine
Application:
61/025,628 →
Providing Trick Mode for Video Stream Transmitted Over Network
Application:
61/025,634 →
Intra Frame Beating Effect Reduction
Application:
61/025,992 →
Macroblock Based Scaling of Images Using Reduced Memory Bandwidth
Application:
61/088,956 →
Efficient Intra Frames Video Coding
Application:
61/094,783 →
Optimized Motion Compensation for Video Coding
Application:
61/103,511 →
Internal Bit Depth Extension and Reference Frame Compression
Application:
61/432,499 →
Internal Bit Depth Extension and Reference Frame Compression for 10-Bit to 8-Bit Compression
Application:
61/452,035 →
Unified Scaling with Differential Coding for Internal Bit Depth Extension and Reference Frame Compression
Application:
61/503,360 →
Unified Scaling with Differential Coding for Internal Bit Depth Extension and Reference Frame Compression
Application:
61/504,087 →
Related Assignments
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Dec 21, 2015
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Patent Release
Dec 21, 2015
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Dec 21, 2015
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Dec 21, 2015
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Dec 21, 2015
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Jan 12, 2016
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Mar 7, 2016
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
Corrective Assignment to Correct the Remove Application 12298143 Previously Recorded on Reel 042985 Frame 0001. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →