IP Library Granted Patent US 6,893,947
Granted Patent B2
US 6,893,947 · App. 10/179,769 · Granted May 17, 2005

Advanced RF enhancement-mode FETs with improved gate properties

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Quick Facts
Patent No.
US 6,893,947
App. No.
10/179,769
Granted
May 17, 2005
Kind
B2
Abstract

A method for fabricating an RF enhancement mode FET ( 30 ) having improved gate properties is provided. The method comprises the steps of providing ( 131 ) a substrate ( 31 ) having a stack of semiconductor layers ( 32-35 ) formed thereon, the stack including a cap layer ( 35 ) and a central layer ( 33 ) defining a device channel, forming ( 103 ) a photoresist pattern ( 58 ) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating ( 105 ) an implant region ( 36, 37 ) in the unmasked region, and (b) removing ( 107 ) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

Claims (48)

1. A method for making an enhancement mode RF device, comprising the steps of:

providing a substrate having a stack of semiconductor layers formed thereon, the stack including a doped cap layer and a central layer defining a device channel;

disposing a mask over the cap layer, thereby defining a masked region and an unmasked region; and

in any order, (a) creating an implant region in the unmasked region, and (b) removing the cap layer from the unmasked region.

2. The method of claim 1 , wherein the mask is a dielectric mask.

3. The method of claim 1 , wherein the mask is a photoresist mask.

4. The method of claim 1 , wherein, after steps (a) and (b) are performed, the implant region and the cap layer region do not substantially overlap.

5. The method of claim 1 , wherein the implant region is created before the cap layer is removed from the unmasked region.

6. The method of claim 1 , wherein the implant region is created after the cap layer is removed from the unmasked region.

7. The method of claim 1 , wherein the stack of semiconductor layers further comprises a source and a drain, wherein the implant region is formed in the stack of semiconductor layers so as to define an implant-free area in the device channel between the source and drain, and wherein the implant-free area is essentially self-aligned with the cap layer.

8. The method of claim 7 , further comprising the steps of:

etching the stack of compound semiconductor layers at the source and drain to form source contact and drain contact areas; and

in any sequence, forming a device insulation structure over the implant-free area and etching a gate opening through the device insulation structure and the cap layer of the stack compound semiconductor layers over the implant-free area.

9. The method of claim 8 , further comprising the step of depositing gate metal in the gate opening to form a gate contact.

10. The method of claim 8 , wherein the stack of compound semiconductor layers includes an electrically insulating layer disposed between the cap layer and the central layer, wherein the stack is etched through the cap layer and partially through the electrically insulating layer, and wherein the method further comprises the step of depositing electrical contacts on the exposed portion of the insulating layer in the source contact area and the drain contact area.

11. The method of claim 1 , wherein the implant region is an N + implant region.

12. The method of claim 1 , wherein the cap layer comprises GaAs.

13. The method of claim 12 , wherein the photoresist mask is removed before steps (a) and (b) are performed.

14. A method for making an enhancement mode RF device, comprising the steps of:

providing a substrate having a stack of semiconductor layers formed thereon, the stack including a doped cap layer and a central layer defining a device channel;

depositing a dielectric layer over the cap layer;

depositing a photoresist over the dielectric layer; and

in any order, (a) forming a dielectric mask out of the dielectric layer, (b) creating an implant region, (c) selectively removing a portion of the cap layer, thereby defining a capped region and an uncapped region, and (d) removing the photoresist;

wherein, after steps (b) and (c) are performed, the implant region and the capped region do not substantially overlap.

15. A method for making an enhancement mode RF device, comprising the steps of:

providing a semiconductor construct having a first layer comprising GaAs disposed over a second layer comprising AlGaAs;

disposing a dielectric layer on the first layer;

forming a photoresist mask over the dielectric layer, thereby defining a first masked region and a first unmasked region, the first unmasked region including a first portion of the first layer;

patterning a hardmask in the dielectric layer, thereby defining a second masked region and a second unmasked region, the second unmasked region including a second portion of the first layer;

removing the photoresist;

creating an N + implant in the second unmasked region; and

removing the first and second portions of the first layer.

16. A method for making an enhancement mode RF device, comprising the steps of:

providing a substrate having a stack of compound semiconductor layers formed thereon, the stack including (a) a doped cap layer, and (b) a central layer defining a device channel; and

implanting a source and drain in the stack of semiconductor layers so as to define an implant-free area in the device channel between the source and drain which substantially coincides with the cap layer.

17. The method of claim 16 , wherein the stack further comprises a buffer, and wherein the source and drain extend at least into the buffer.

18. The method of claim 17 , further comprising the steps of, in any sequence, forming a device insulation structure over the implant-free area, and etching a gate opening through the device insulation structure and the cap layer of the stack compound semiconductor layers in the implant-free area, the gate opening being spaced from the source and the drain.

19. A method for making an enhancement mode RF device, comprising the steps of:

providing a substrate having a stack of semiconductor layers formed thereon, the stack including doped a cap layer and a central layer defining a device channel;

disposing a first mask over the cap layer, thereby defining a first masked region and a first unmasked region;

in any order, (a) creating an implant region in the first unmasked region, and (b) removing the cap layer from the first unmasked region;

removing the first mask;

disposing a second mask, distinct from said first mask, over the cap layer, thereby defining a second masked region and a second unmasked region; and

forming a gate opening through the cap layer in the second unmasked region.

20. The method of claim 9 , wherein the implant region comprises a source and a drain, and wherein the gate is disposed between the source and drain.

21. The method of claim 1 , wherein the cap layer and the implant region are not in physical contact.

22. The method of claim 14 , wherein the cap layer and the implant region are not in physical contact.

23. The method of claim 16 , wherein the cap layer is not in physical contact with either the source or the drain.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →