Granted Patent B2

US 8,643,066 · App. 12/251,746 · Granted Feb 4, 2014

Abstract

Claims (11)

1. A SRAM bitcell comprising:

a pull-down transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region;

a pull-up transistor with a vertical active region without a horizontal active region; and

a pass-gate transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

2. The SRAM bitcell of claim 1 , wherein a perimeter of a channel of the pull-down transistor is greater than a perimeter of a channel of the pull-up transistor and the pass-gate transistor.

3. The SRAM bitcell of claim 1 , wherein the pull-down transistor has a gate length smaller than a gate length of the pull-up transistor or a gate length of the pass-gate transistor.

4. The SRAM bitcell of claim 1 , wherein a drain region of the pull-down transistor and a drain region of the pull-up transistor are connected using a contiguous silicon region, which connects the horizontal active region and the vertical active region of the pull-down transistor to the vertical active region of the pull-up transistor.

5. The SRAM bitcell of claim 1 , wherein the pull-down transistor and the pull-up transistor share a common gate electrode.

6. The SRAM bitcell of claim 1 , wherein the pull-up transistor is a p-channel transistor.

7. The SRAM bitcell of claim 1 wherein a threshold voltage of the pull-up transistor is set to a lower value than a threshold voltage of the pass-gate transistor.

8. The SRAM bitcell of claim 7 , wherein the threshold voltage of the pull-up transistor is set by adjusting at least one of a width of the vertical active region and a height of the horizontal active region.

Assignments (30)