IP Library Granted Patent US 8,526,708
Granted Patent B2
US 8,526,708 · App. 12/526,445 · Granted Sep 3, 2013

Measurement of critical dimensions of semiconductor wafers

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Quick Facts
Patent No.
US 8,526,708
App. No.
12/526,445
Granted
Sep 3, 2013
Kind
B2
Abstract

A semiconductor wafer critical dimension measurement method comprising receiving an image of a site of the semiconductor wafer comprising a plurality of features, processing the image to measure at least one critical dimension of at least some of the features, analyzing the critical dimension of each feature and determining the feature to be a non-defective feature or a defective feature, and using the critical dimension of at least some of any non-defective features as a measure of the critical dimension of features of the semiconductor wafer.

Claims (29)

1. A semiconductor wafer critical dimension measurement method, comprising

receiving an image of a site of the semiconductor wafer comprising a plurality of features,

processing the image to measure at least one critical dimension of at least some of the features,

analysing, by a processor, the critical dimension of each feature and determining the feature to be a non-defective feature or a defective feature, and

using the critical dimensions of at least some of any non-defective features as a measure of the critical dimensions of features of the semiconductor wafer,

using the measure of the critical dimensions of features of the semiconductor wafer to control fabricating the wafer,

wherein analysing the critical dimension of a feature and determining the feature to be a non-defective feature or a defective feature, comprises comparing the critical dimension of the feature with the critical dimensions of a plurality of other features and determining the feature to be a non-defective feature if the critical dimension of the feature is substantially equal to the critical dimensions of a majority of the other features, and determining the feature to be a defective feature if the critical dimension of the feature is not substantially equal to the critical dimensions of a majority of the other features.

2. A method as claimed in claim 1 , wherein the site is a site reviewed in a defect review in a fabrication process of the wafer, and the image of the site is produced in the defect review.

3. A method as claimed in claim 1 , wherein the site is a site which has been pre-chosen for critical dimension measurement.

4. A method as claimed in claim 1 , wherein processing the image to measure the critical dimension of at least some of the features comprises drawing a contour around each feature, determining the critical dimension of the contour, and using this as a measurement of the critical dimension of the feature.

5. A method as claimed in claim 1 , wherein the image is processed to measure the critical dimension of at least some features which are completely contained in the image.

6. A method as claimed in claim 1 , wherein analysing the critical dimension of a feature and determining the feature to be a non-defective feature or a defective feature, further comprises comparing the critical dimension of the feature with a pre-defined critical dimension range, and determining the feature to be a non-defective feature if the critical dimension of the feature lies within the pre-defined critical dimension range, and determining the feature to be a defective feature if the critical dimension of the feature lies outside the pre-defined critical dimension range.

7. A method as claimed in claim 1 , wherein using the critical dimensions of at least some of any non-defective features as a measure of the critical dimensions of features of the semiconductor wafer, comprises calculating an average critical dimension of the non-defective features and using the average critical dimension as a measure of the critical dimensions of features of the semiconductor wafer.

8. A method as claimed in claim 7 , comprising, for each of a plurality of sites of the wafer, calculating an average critical dimension of the non-defective features of the site, and using the average critical dimension of the sites as a measure of the critical dimensions of features of the semiconductor wafer.

9. A method as claimed in claim 7 , wherein the at least one critical dimension which is measured comprises any of the width, height, shape, topographic features, line edge roughness, volume of a feature of the wafer.

10. A semiconductor wafer critical dimension measurement system, comprising

a receiver which receives an image of a site of the semiconductor wafer comprising a plurality of features,

a processor which processes the image to measure at least one critical dimension of at least some of the features,

an analyser which analyses the critical dimension of each feature, determines the feature to be a non-defective feature or a defective feature, and uses the critical dimension of at least some of any non-defective features as a measure of the critical dimension of features of the semiconductor wafer, wherein analysing the critical dimension of a feature and determining the feature to be a non-defective feature or a defective feature, comprises comparing the critical dimension of the feature with the critical dimensions of a plurality of other features and determining the feature to be a non-defective feature if the critical dimension of the feature is substantially equal to the critical dimensions of a majority of the other features, and determining the feature to be a defective feature if the critical dimension of the feature is not substantially equal to the critical dimensions of a majority of the other features.

11. A method as claimed in claim 2 , wherein processing the image to measure the critical dimension of at least some of the features comprises drawing a contour around each feature, determining the critical dimension of the contour, and using this as a measurement of the critical dimension of the feature.

12. A method as claimed in claim 2 , wherein the image is processed to measure the critical dimension of at least some features which are completely contained in the image.

13. A method as claimed in claim 4 , wherein the image is processed to measure the critical dimension of at least some features which are completely contained in the image.

14. A method as claimed in claim 4 , wherein analysing the critical dimension of a feature and determining the feature to be a non-defective feature or a defective feature, further comprises comparing the critical dimension of the feature with a pre-defined critical dimension range, and determining the feature to be a non-defective feature if the critical dimension of the feature lies within the pre-defined critical dimension range, and determining the feature to be a defective feature if the critical dimension of the feature lies outside the pre-defined critical dimension range.

15. A method as claimed in claim 4 , wherein the at least one critical dimension which is measured comprises any of the width, height, shape, topographic features, line edge roughness, volume of a feature of the wafer.

16. A method as claimed in claim 5 , wherein the at least one critical dimension which is measured comprises any of the width, height, shape, topographic features, line edge roughness, volume of a feature of the wafer.

17. A method as claimed in claim 5 , wherein analysing the critical dimension of a feature and determining the feature to be a non-defective feature or a defective feature, further comprises comparing the critical dimension of the feature with a pre-defined critical dimension range, and determining the feature to be a non-defective feature if the critical dimension of the feature lies within the pre-defined critical dimension range, and determining the feature to be a defective feature if the critical dimension of the feature lies outside the pre-defined critical dimension range.

18. A method as claimed in claim 6 , wherein using the critical dimensions of at least some of any non-defective features as a measure of the critical dimensions of features of the semiconductor wafer, comprises calculating an average critical dimension of the non-defective features and using the average critical dimension as a measure of the critical dimensions of features of the semiconductor wafer.

19. A method as claimed in claim 1 , wherein using the measure of the critical dimensions of the features of the semiconductor wafer to control fabricating the wafer includes scrapping a wafer, stopping the fabrication process, or processing a wafer using a changed fabrication process parameter.

20. A method as claimed in claim 19 , wherein using the measure of the critical dimensions of the features of the semiconductor wafer to control fabricating the wafer includes processing a wafer using a changed fabrication process parameter.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0854 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →