Transistor and method with dual layer passivation
View Patent ↗Semiconductor devices ( 61 ) and methods ( 80 - 89, 100 ) are provided with dual passivation layers ( 56, 59 ). A semiconductor layer ( 34 ) is formed on a substrate ( 32 ) and covered by a first passivation layer (PL- 1 ) ( 56 ). PL- 1 ( 56 ) and part ( 341 ) of the semiconductor layer ( 34 ) are etched to form a device mesa ( 35 ). A second passivation layer (PL- 2 ) ( 59 ) is formed over PL- 1 ( 56 ) and exposed edges ( 44 ) of the mesa ( 35 ). Vias ( 90, 92, 93 ) are etched through PL- 1 ( 56 ) and PL- 2 ( 59 ) to the semiconductor layer ( 34 ) where source ( 40 ), drain ( 42 ) and gate are to be formed. Conductors ( 41, 43, 39 ) are applied in the vias ( 90, 92, 93 ) for ohmic contacts for the source-drain ( 40, 42 ) and a Schottky contact ( 39 ) for the gate. Interconnections ( 45, 47 ) over the edges ( 44 ) of the mesa ( 35 ) couple other circuit elements. PL- 1 ( 56 ) avoids adverse surface states ( 52 ) near the gate and PL- 2 ( 59 ) insulates edges ( 44 ) of the mesa ( 35 ) from overlying interconnections ( 45, 47 ) to avoid leakage currents ( 46 ). An opaque alignment mark ( 68 ) is desirably formed at the same time as the device ( 61 ) to facilitate alignment when using transparent semiconductors ( 34 ).
1. A method for forming a semiconductor device on a substrate having a principal surface, the method comprising:
forming a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer has an outer surface opposite the substrate;
forming a first passivation layer on the outer surface of the semiconductor layer opposite the substrate by providing a layer comprising silicon and nitrogen;
locally etching away portions of the first passivation layer and the semiconductor layer to thereby form a device mesa above the principal surface of the substrate, wherein the device mesa has an upper surface still covered by the first passivation layer and wherein the device mesa further has exposed lateral edges where the first passivation layer and the semiconductor layer has been removed;
after the etching step, forming a second passivation layer at least over the first passivation layer on the upper surface of the device mesa and the exposed lateral edges of the device mesa, wherein the second passivation layer is a single and substantially contiguous layer that continuously extends across the entire upper surface of the device mesa and that also completely covers the exposed lateral edges of the device mesa;
after forming the second passivation layer, providing source-drain vias and a gate via through the first and second passivation layers to the upper surface of the semiconductor layer on the device mesa; and
forming conductors in the vias so as to provide ohmic contact to the semiconductor layer in the source-drain vias and a Schottky contact to the semiconductor layer in the gate via.
2. A method for forming a semiconductor device on a substrate having a principal surface, the method comprising:
forming a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer has an outer surface opposite the substrate;
forming a first passivation layer on the outer surface of the semiconductor layer opposite the substrate;
locally etching away portions of the first passivation layer and the semiconductor layer to thereby form a device mesa above the principal surface of the substrate, wherein the step of locally etching portions of the first passivation layer and the semiconductor layer further comprises at the same time also forming one or more alignment mesas located a pre-determined distance from the device mesa, wherein the device mesa has an upper surface still covered by the first passivation layer and wherein the device mesa further has exposed lateral edges where the first passivation layer and the semiconductor layer has been removed;
after the etching step, forming a second passivation layer at least over the first passivation layer on the upper surface of the device mesa and the exposed lateral edges of the device mesa, wherein the second passivation layer is a single and substantially contiguous layer that continuously extends across the entire upper surface of the device mesa and that also completely covers the exposed lateral edges of the device mesa;
after forming the second passivation layer, providing source-drain vias and a gate via through the first and second passivation layers to the upper surface of the semiconductor layer on the device mesa; and
forming conductors in the vias so as to provide ohmic contact to the semiconductor layer in the source-drain vias and a Schottky contact to the semiconductor layer in the gate via.
3. The method of claim 2 , further comprising before the step of forming the second passivation layer, providing an alignment region of an optically opaque material on at least some of the one or more alignment mesas.
4. The method of claim 3 , wherein the step of providing source-drain and gate vias further comprises forming an alignment pattern in at least one of the one or more alignment mesas at the same time as opening the source-drain vias or the gate via.
5. The method of claim 1 , where the step of forming the semiconductor layer comprises, forming a layer comprising a III-V compound.
6. The method of claim 1 , wherein the step of forming the semiconductor layer comprises, forming a layer comprising GaN.
7. The method of claim 1 , wherein the step of forming the second passivation layer comprises, providing a layer comprising silicon and nitrogen.
8. The method of claim 1 , wherein the step of forming conductors in the vias comprises forming source-drain contacts comprising aluminum.
9. The method of claim 1 , wherein the step of forming conductors in the vias comprises forming a gate conductor comprising Ni or Pt.
10. A method of forming an alignment mark associated with a semiconductor device, comprising:
providing a substrate having a principal surface;
forming a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer is substantially optically transparent at a wavelength used for alignment and has an outer surface;
providing a first dielectric layer on the outer surface;
locally etching portions of the first dielectric layer and the semiconductor layer to form a device region and an alignment region above the principal surface, wherein the device region comprises an upper surface covered by the first dielectric layer with exposed lateral edges where the first dielectric layer and the semiconductor layer have been removed;
forming an optically opaque region on the alignment region, wherein the optically opaque region is optically opaque at the wavelength used for alignment;
forming a second dielectric layer over the device region and the optically opaque region on the alignment region, wherein the second dielectric layer is a single and substantially contiguous layer that continuously covers the entire upper surface of the device region and that also completely covers the exposed lateral edges of the device region; and
forming an alignment pattern in the second dielectric layer on the alignment region at the same time as opening one or more vias in the dielectric layers on the device region.
11. The method of claim 10 , wherein the step of forming the semiconductor layer comprises forming a layer of GaN.
12. The method of claim 10 , wherein the step of forming the optically opaque region comprises forming a region comprising silicon.
13. The method of claim 10 , wherein the step of providing the first dielectric layer comprises, forming a layer comprising Si 3 N 4 , SiO 2 , SiO x N y , AlN, or Al 2 O 3 , or combinations or mixtures thereof.
14. The method of claim 10 , wherein the step of forming the second dielectric layer comprises forming a layer comprising Si 3 N 4 , SiO 2 , SiO x N y , AlN, or Al 2 O 3 , or combinations or mixtures thereof.
15. The method of claim 10 , wherein the step of forming an alignment pattern in the second dielectric layer on the alignment region, comprises etching away portions of the second dielectric layer and part of the optically opaque region.
16. A method for forming a semiconductor device on a substrate having a principal surface, the method comprising:
forming a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer has an outer surface opposite the substrate;
forming a first passivation layer on the outer surface of the semiconductor layer opposite the substrate;
locally etching away portions of the first passivation layer and the semiconductor layer to thereby form a device mesa above the principal surface of the substrate, wherein the device mesa has an upper surface still covered by the first passivation layer and wherein the device mesa further has exposed lateral edges where the first passivation layer and the semiconductor layer has been removed;
after the etching step, forming a second passivation layer at least over the first passivation layer on the upper surface of the device mesa and the exposed lateral edges of the device mesa, wherein the second passivation layer is a single and substantially contiguous layer that continuously extends across the entire upper surface of the device mesa and that also completely covers the exposed lateral edges of the device mesa, and wherein the first and second passivation layers are formed of the same material;
after forming the second passivation layer, providing source-drain vias and a gate via through the first and second passivation layers to the upper surface of the semiconductor layer on the device mesa; and
forming conductors in the vias so as to provide ohmic contact to the semiconductor layer in the source-drain vias and a Schottky contact to the semiconductor layer in the gate via.
17. A method for forming a semiconductor device on a substrate having a principal surface, the method comprising:
forming a semiconductor layer on the principal surface of the substrate, wherein the semiconductor layer has an outer surface opposite the substrate;
forming a first passivation layer on the outer surface of the semiconductor layer opposite the substrate by providing a layer comprising silicon and nitrogen;
locally etching away portions of the first passivation layer and the semiconductor layer to thereby form a device mesa above the principal surface of the substrate, wherein the device mesa has an upper surface still covered by the first passivation layer and wherein the device mesa further has exposed lateral edges where the first passivation layer and the semiconductor layer has been removed;
after the etching step, forming a second passivation layer at least over the first passivation layer on the upper surface of the device mesa and the exposed lateral edges of the device mesa, wherein the second passivation layer is a single and substantially contiguous layer that continuously extends across the entire upper surface of the device mesa and that also completely covers the exposed lateral edges of the device mesa;
after forming the second passivation layer, providing source-drain vias and a gate via through the first and second passivation layers to the upper surface of the semiconductor layer on the device mesa; and
forming conductors in the vias so as to provide contact to the semiconductor layer in the source-drain vias and in the gate via.