Non-volatile memory cell
View Patent ↗A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode, and a second transistor having a first current electrode connected to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode. By applying a read signal to the control electrode of the first transistor, the state of the cell (blown or unblown) is read.
1. A device comprising:
a programmable fuse having a first terminal coupled to a first reference, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode; and
a second transistor having a first current electrode connected to the first reference, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode;
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control terminal to receive a control signal, and a second, current electrode; and
a trimmable module, wherein the trimmable module has been manufactured using a first manufacturing process, and wherein the first transistor, the second transistor, and the third transistor have been manufactured using the first manufacturing process.
2. The device of claim 1 , wherein the trimmable module is a clock generator module.
3. The device of claim 1 , wherein the trimmable module is an analog module.
4. The device of claim 1 , wherein the trimmable module is an identification module.
5. The device of claim 1 , wherein the manufacturing process is a CMOS process.
6. A device, comprising:
a programmable fuse having a first terminal coupled to a first reference, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode;
a second transistor having a first current electrode coupled to the first reference, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode; and
a trimmable module coupled to the second terminal of the programmable fuse.
7. The device of claim 6 , wherein the trimmable module, the first transistor, and the second transistor have been manufactured using a first manufacturing process.
8. The device of claim 6 , further comprising:
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control terminal to receive a control signal, and a second current electrode.
9. The device of claim 8 , further comprising:
a fourth transistor having a first current electrode coupled to a first reference voltage, a control electrode to receive a read signal, and a second current electrode coupled to the control electrode of the third transistor.
10. A device, comprising:
a programmable fuse having a first terminal coupled to a first reference, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode;
a second transistor having a first current electrode connected to the first reference, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode;
a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control terminal to receive a control signal, and a second current electrode;
a cell read circuit coupled to the control electrode of the third transistor; and
a fourth transistor having a first current electrode coupled to a first reference voltage, a control electrode to receive a read signal, and a second current electrode coupled to the control electrode of the third transistor.
11. The device of claim 10 , further comprising:
a fifth transistor having a first current electrode coupled to the control electrode of the second transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to a second reference;
a sixth transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrode of the third transistor, and a second current electrode coupled to the second reference; and
a seventh transistor having a first current electrode coupled to the control electrode of the third transistor, a control electrode to receive the read signal, and a second current electrode coupled to the second reference.