Testing non-volatile memory devices for charge leakage
View Patent ↗The method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm.
1. A method of testing a floating gate non-volatile memory semiconductor device including an array of cells including floating gates for storing data in the form of electrical charge and insulating material for insulating said floating gates, the method comprising:
applying a test pattern of said electrical charge to the floating gates;
exposing the device to energy to accelerate leakage of the electrical charges out of the cells; and
subsequently comparing the remaining electrical charges in the cells to the test pattern, wherein said energy comprises electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss through said insulating material by a tunnel-effect mechanism from the floating gates of defective cells relative to charge loss from non-defective cells.
2. The method of testing a non-volatile memory semiconductor device as claimed in claim 1 , wherein said radiation penetrates through said floating gate to excite said charges to said energy level sufficient for accelerating charge loss from defective cells by said tunnel-effect mechanism.
3. The method of testing a non-volatile memory semiconductor device as claimed in claim 1 , wherein said floating gates comprise Silicon.
4. The method of testing a non-volatile memory semiconductor device as claimed in claim 3 , wherein said floating gates comprise Polysilicon.
5. The method of testing a non-volatile memory semiconductor device as claimed in claim 1 , wherein the wavelength of said radiation is in the visible range.
6. The method of testing a non-volatile memory semiconductor device as claimed in claim 4 , wherein the wavelength of said radiation is in the range of 440 to 560 nm.
7. The method of testing a non-volatile memory semiconductor device as claimed in claim 6 , wherein the wavelength of said radiation is in the range of 480 to 520 nm.
8. The method of testing a non-volatile memory semiconductor device as claimed in claim 1 , wherein each of said cells comprises:
a lateral transistor having source and drain regions at a face of a semiconductive substrate;
said floating gate at being juxtaposed with the transistor;
said insulating material comprising:
a layer at the face of the substrate insulating the floating gate from the transistor;
a control gate being in capacitive coupling with the floating gate;
said radiation passing through said floating gate to access the parts of said devices to be tested adjacent said face.
9. A method of producing a wafer comprising an array of non-volatile memory floating gate semiconductor devices, including a testing step of testing the devices by the method as claimed in claim 1 .
10. A method of producing non-volatile memory semiconductor dice, including a testing step of testing by the method as claimed in claim 1 .
11. An apparatus for testing a floating gate non-volatile memory semiconductor device including an array of cells including floating gates for storing data in the form of electrical charge and insulating material for insulating said floating gates, the apparatus comprising:
probe means for applying a test pattern of said electrical charge to the floating gates and for subsequently detecting the remaining electrical charges in the cells for comparison with the test pattern; exposure means for exposing the device to energy to accelerate leakage of the applied electrical charges out of the cells before comparison with the test pattern, said energy to which said exposure means is arranged to expose the device comprising electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss through said insulating material by a tunnel-effect mechanism from the floating gates of defective cells relative to charge loss from non-defective cells.
12. The apparatus for testing a non-volatile memory semiconductor device as claimed in claim 11 , wherein the wavelength of said radiation is in the visible range.
13. The apparatus for testing a non-volatile memory semiconductor device as claimed in claim 12 , wherein the wavelength of said radiation is in the range of 440 to 560 nm.
14. The apparatus for testing a non-volatile memory semiconductor device as claimed in claim 13 , wherein the wavelength of said radiation is in the range of 480 to 520 nm.
15. The method of testing a non-volatile memory semiconductor device as claimed in claim 2 , wherein said floating gates comprise Silicon.
16. The method of testing a non-volatile memory semiconductor device as claimed in claim 3 , wherein the wavelength of said radiation is in the visible range.
17. The method of testing a non-volatile memory semiconductor device as claimed in claim 4 , wherein the wavelength of said radiation is in the visible range.
18. The method of testing a non-volatile memory semiconductor device as claimed in claim 2 , wherein the wavelength of said radiation is in the visible range.
19. The method of testing a non-volatile memory semiconductor device as claimed in claim 2 , wherein each of said cells comprises:
a lateral transistor having source and drain regions at a face of a semiconductive substrate;
said floating gate being juxtaposed with the transistor;
said insulating material comprising:
a layer at the face of the substrate insulating the floating gate from the transistor;
a control gate being in capacitive coupling with the floating gate;
said radiation passing through said floating gate to access the parts of said devices to be tested adjacent said face.
20. The method of testing a non-volatile memory semiconductor device as claimed in claim 3 , wherein each of said cells comprises:
a lateral transistor having source and drain regions at a face of a semiconductive substrate;
said floating gate being juxtaposed with the transistor;
said insulating material comprising:
a layer at the face of the substrate insulating the floating gate from the transistor;
a control gate being in capacitive coupling with the floating gate;
said radiation passing through said floating gate to access the parts of said devices to be tested adjacent said face.