Patent Assignment
Reel/Frame 037354/0757
Patent Release
Recorded: 2015-12-21
Pages: 16
Assignor
CITIBANK, N.A., AS COLLATERAL AGENT
Executed: 2015-12-07
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TEXAS, 78735
Covered Properties
(238)
Magnetic Nanomaterials and Synthesis Method
Programmable Phase Mapping and Phase Rotation Modulator and Method
Multi-Mode Method and Apparatus for Performing Digital Modulation and Demodulation
Method and Apparatus for Rf Carrier Feedthrough Suppression
Method and Apparatus to Perform Battery Charging Using a Dc-Dc Converter Circuit
Ultra Wideband Communication System, Method, and Device with Low Noise Pulse Formation
System and Method to Initialize a Multiple Function Device with a Multi-Part Boot Algorithm
Use of Multiple Overlays to Import Programs from External Memory
Hardware for Performing an Arithmetic Function
Btsc Encoder and Integrated Circuit
Autonomous Memory Checker for Runtime Security Assurance and Method Therefore
Method and Apparatus for Endianness Control in a Data Processing System
System and Method of Reading Non-Volatile Computer Memory
Receiver for a Wireless Communication Device
Compact Radio Frequency Harmonic Filter Using Integrated Passive Device Technology
Decoder with M-at-a-Time Traceback
Method of Making a Nitrided Gate Dielectric
Method of Forming a Semiconductor Device Having a Diffusion Barrier Stack and Structure Thereof
Electronic Device Including an Array and Process for Forming the Same
System and Method for Predicting Rotational Imbalance
System and Method for Unified Cache Access Using Sequential Instruction Information
Method for Forming an Electronic Device
Ultra Wide Bandwidth Spread-Spectrum Communications System
Leakage Nulling Receiver Correlator Structure and Method for Ultra Wide Bandwidth Communication System
Programmable Structure Including Discontinuous Storage Elements and Spacer Control Gates in a Trench
Semiconductor Devices and Method of Fabrication
Wide and Narrow Trench Formation in High Aspect Ratio Mems
Wideband Variable Gain Amplifier in an Ultra Wideband Receiver
Process of Making a Iii-V Compound Semiconductor Heterostructure Mosfet
Method for Forming Microelectronic Assembly
System and Methods for Accessing Solid-State Memory Devices
Linearized and Balanced Mixer Apparatus and Signal Mixing Method
Method and Apparatus for Performing Test Pattern Autograding
Electronic Device Including a Transistor Structure Having an Active Region Adjacent to a Stressor Layer and a Process for Forming the Electronic Device
Programmable Infrared Data Processor
Method of Separating a Structure in a Semiconductor Device
Class-D Amplifier with Noise-Immunity Feedback
Electronic Device Including a Static-Random-Access Memory Cell and a Process of Forming the Electronic Device
Method for Forming Multi-Layer Bumps on a Substrate
System and Method for Reducing the Power Consumption of Clock Systems
Methods and Apparatus for Thermal Isolation in Vertically-Integrated Semiconductor Devices
Clock Generation Circuit
Semiconductor Device Packaging
Switch Device and Method
High Linearity and Low Noise Amplifier with Continuously Variable Gain Control
Process of Forming an Electronic Device Including a Semiconductor Island Over an Insulating Layer
Process of Forming an Electronic Device Including a Semiconductor Fin
Selective Cache Line Allocation Instruction Execution and Circuitry
Non-Volatile Memory Wih Controlled Program/Erase
Memory with Clocked Sense Amplifier
Method of Making a Multiple Crystal Orientation Semiconductor Device
Composite Capacitor and Method for Forming the Same
Method for Cleaning Electroless Process Tank
Processor and Method for Altering Address Translation
Differential Receiver Circuit
Methods and Apparatus for Thermal Management in a Multi-Layer Embedded Chip Structure
Coil-Less Overtone Crystal Oscillator
Overtone Crystal Oscillator Automatic Calibration System
Storage Circuit with Efficient Sleep Mode and Method
Concurrent Programming and Program Verification of Floating Gate Transistor
Power Supply Circuit
Digital Clock Frequency Multiplier
Dynamic Scannable Latch and Method of Operation
Latching Input Buffer Circuit with Variable Hysteresis
Communication Steering for Use in a Multi-Master Shared Resource System
Anneal of Epitaxial Layer in a Semiconductor Device
Clock Jitter Minimization in a Continuous Time Sigma Delta Analog-to-Digital Converter
Level Shifter Circuit
Multiple Block Memory with Complementary Data Path
Patent:
7,397,722 →
Application:
11/670,632 →
Dotted Channel Mosfet and Method
Method for Forming a Split Gate Memory Device
Multi-Strand Substrate for Ball-Grid Array Assemblies and Method
Series Regulator Circuit
Method and System of Operating Mode Detection
Methodology to Reduce Soi Floating-Body Effect
Patent:
7,410,876 →
Application:
11/784,561 →
Miller Capacitance Tolerant Buffer Element
Voltage Regulator and Method for Providing a Regulated Output
Patent:
7,423,416 →
Application:
11/853,939 →
Method for Synchronizing a Transmission of Information and a Device Having Synchronizing Capabilities
Method for Managing Under-Runs and a Device Having Under-Run Management Capabilities
Method for High Speed Framing and a Device Having Framing Capabilities
Device and Method for Evaluating Electrostatic Discharge Protection Capabilities
Controlling the Access of Master Elements to Slave Elements Over a Communication Bus
Device and Method for Finding Extreme Values in a Data Block
Hardware Accelerator Based Method and Device for String Searching
Regulated Voltage System and Method of Protection Therefor
Device Having Data Sharing Capabilities and a Method for Sharing Data
Method and Apparatus for Conditioning a Cmp Pad
"Universal" Barrier Cmp Slurry for Use with Low Dielectric Constant Interlayer Dielectrics
Application:
12/162,173 →
Publication:
US 2009/0045164
Device and Method for Adding and Subtracting Two Variables and a Constant
Application:
12/162,174 →
Publication:
US 2009/0006822
Barrier Slurry Compositions and Barrier Cmp Methods
Application:
12/162,177 →
Publication:
US 2009/0209103
Device and a Method for Estimating Transistor Parameter Variations
Vendor Independent Method to Merge Coverage Results for Different Designs
Multi-Exposure Lithography Employing a Single Anti-Reflective Coating Layer
Integrated Conformal Shielding Method and Process Using Redistributed Chip Packaging
Spool Braking Device for Fishing Reel
Pre-Driver for Bridge Circuit
Dual Metal Gate Transistor with Resistor Having Dielectric Layer Between Metal and Polysilicon
Application:
12/171,733 →
Publication:
US 2010/0006841
Electronic Device Including a Semiconductor Fin
Authentication System Including Electric Field Sensor
Method to Reduce Threshold Voltage (Vt) in Silicon Germanium (Sige), High-K Dielectric-Metal Gate, P-Type Metal Oxide Semiconductor Field Effect Transistors
Semiconductor Device and Method of Making Same
Application:
12/176,914 →
Publication:
US 2009/0095983
Semiconductor Resistor Formed in Metal Gate Stack
Buried Asymmetric Junction Esd Protection Device
Dynamic Address-Type Selection Control in a Data Processing System
Debug Trace Messaging with One or More Characteristic Indicators
Debug Message Generation Using a Selected Address Type
System, Method and Computer Program Product for Executing a High Level Programming Language Conditional Statement
System and Method for Providing a Blended Picture
System and Method for Arbitrating Between Memory Access Requests
Method for Generating a Output Clock Signal Having a Output Cycle and a Device Having a Clock Signal Generating Capabilities
Integrated Circuit and a Method for Recovering from a Low-Power Period
Device and Method for Evaluating a Temperature
System and Method for Power Management
Phase-Locked Loop System with a Phase-Error Spreading Circuit
Electronic Device Including a Transistor Structure Having an Active Region Adjacent to a Stressor Layer
Baseband Filters for Use in Wireless Communication Devices
Stacked Cascode Current Source
Branch Target Buffer Allocation
System and Method for Fetching Information to a Cache Module Using a Write Back Allocate Algorithm
Self-Aligned in-Laid Split Gate Memory and Method of Making
Gui-Facilitated Change Management for Vehicle Electrical/Electronic Architecture Design
Gui-Facilitated Simulation and Verification for Vehicle Electrical/Electronic Architecture Design
Application:
12/181,828 →
Publication:
US 2010/0030546
Complexity Management for Vehicle Electrical/Electronic Architecture Design
Method for Forming an Insulated Gate Field Effect Device
Dual Current Path Ldmosfet with Graded Pbl for Ultra High Voltage Smart Power Applications
Semiconductor Devices with Extended Active Regions
Led Driver with Frame-Based Dynamic Power Management
Square to Pseudo-Sinusoidal Clock Conversion Circuit and Method
Double-Balanced Sinusoidal Mixing Phase Interpolator Circuit and Method
Clocked Single Power Supply Level Shifter
Balun Signal Transformer and Method of Forming
Method of Providing a Data Signal for Channel Estimation and Circuit Thereof
Integrated Circuit Having an Array Supply Voltage Control Circuit
Packaging an Integrated Circuit Die with Backside Metallization
Lithography for Pitch Reduction
Microelectronic Assembly
Echo Canceller with Heavy Double-Talk Estimation
Method for Managing Branch Instructions and a Device Having Branch Instruction Management Capabilities
Techniques for Calibrating a Transceiver of a Communication Device
Provision of Extended Addressing Modes in a Single Instruction Multiple Data (Simd) Data Processor
Management of Arq Detection Threshold in Communication Networks
Management of Power Domains in an Integrated Circuit
Transistor with Gain Variation Compensation
Method for Address Comparison and a Device Having Address Comparison Capabilities
Method for Speculative Execution of Instructions and a Device Having Speculative Execution Capabilities
Method for Executing an Instruction Loop and a Device Having Instruction Loop Execution Capabilities
Audio Signal Processing System and Method
Gain Controlled Threshold in Denoising Filter for Image Signal Processing
Debug Instruction for Execution by a First Thread to Generate a Debug Event in a Second Thread to Cause a Halting Operation
Debug Instruction for Use in a Multi-Threaded Data Processing System
Application:
12/195,225 →
Publication:
US 2010/0049956
Device That Can Be Rendered Useless and Method Thereof
Techniques for Adaptive Predistortion Direct Current Offset Correction in a Transmitter
Data Processing Device Design Tool and Methods
Method for Detecting Output Short Circuit in Switching Regulator
Circuit for Detecting Bonding Defect in Multi-Bonding Wire
Method for Testing H-Bridge
Receiver I/Q Group Delay Mismatch Correction
Memory Device and Method Thereof
Electronic Device Including a Gated Diode
Pressure Sensor Featuring Offset Cancellation and Method of Making
Cache Snoop Limiting Within a Multiple Master Data Processing System
Snoop Request Arbitration in a Data Processing System
Synchronization Mechanism for Use with a Snoop Queue
Snoop Request Arbitration in a Data Processing System
Package Device Having Crack Arrest Feature and Method of Forming
System and Method for Cooling Using Impinging Jet Control
Handheld Device for Transmitting a Visual Format Message
Application:
12/203,480 →
Publication:
US 2008/0317226
Semiconductor Device with a Buffer Region with Tightly-Packed Filler Particles
Method of Forming Ball Bond
Application:
12/204,810 →
Publication:
US 2010/0059883
Phase/Frequency Detector for a Phase-Locked Loop That Samples on Both Rising and Falling Edges of a Reference Signal
Method for Estimating Channel Statistics in an Ofdm Receiver
Selective Cache Way Mirroring
Error Detection Schemes for a Unified Cache in a Data Processing System
Error Detection Schemes for a Cache in a Data Processing System
Power Mosfet with a Gate Structure of Different Material
Circuit and Method for Optimizing Memory Sense Amplifier Timing
Methods for Forming Varactor Diodes
Counter-Doped Varactor Structure and Method
System and method for providing external power on a universal serial bus
Capacitive Detector
Application:
12/207,513 →
Publication:
US 2009/0095080
Methods for Forming Quad Flat No-Lead (Qfn) Packages
Method for Power Reduction and a Device Having Power Reduction Capabilities
Memory with Level Shifting Word Line Driver and Method Thereof
Ultra-Thin Die and Method of Fabricating Same
Fourier Transform Processing and Twiddle Factor Generation
Flexible Carrier for High Volume Electronic Package Fabrication
Error Correcting Viterbi Decoder
Digital Complex Tone Generator and Corresponding Methods
Recovering Symbols in a Communication Receiver
Integrated Circuit Having Boosted Array Voltage and Method Therefor
Memory Having Self-Timed Bit Line Boost Circuit and Method Therefor
Method and Apparatus for Configuring a Unified Cache Based on an Associated Error Rate
Method and Apparatus for Managing Cache Reliability Based on an Associated Error Rate
Method of Forming Semiconductor Package
Effective Efuse Structure
Method of Forming a Semiconductor Package Including Two Devices
Method of Forming a Package with Exposed Component Surfaces
Method of Forming a Gate Dielectric by in-Situ Plasma
Split-Gate Non-Volatile Memory Cell and Method
Method and Apparatus for Testing Data Converter
Data Conversion Circuitry for Converting Analog Signals to Digital Signals and Vice-Versa and Method Therefor
Method for Transistor Fabrication with Optimized Performance
Data Conversion Circuitry Having Successive Approximation Circuitry and Method Therefor
Data Conversion Circuitry with an Extra Successive Approximation Step and Method Therefor
Self-Calibrating Data Conversion Circuitry and Method Therefor
Dual-Loop Dc-to-Dc Converter Apparatus
Integrated Circuit Module with Integrated Passive Device
Method of Packaging a Semiconductor Die
Application:
12/242,622 →
Publication:
US 2009/0023248
Electronic Device Having a Memory Element and Method of Operation Therefor
Acceleration Sensor Arrangement, Safing Arrangement for an Activation System, Activation System
Electronic Apparatus and Method of Conserving Energy
Method for Exchanging Information with Physical Layer Component Registers
Lin Bus Network, Integrated Circuit and Method of Communicating Thereon
Device and Method for Testing a Noise Immunity Characteristic of Analog Circuits
Method for Scheduling Atm Cells and a Device Having Atm Cell Scheduling Capabilities
Method of Patterning a Layer Using a Pellicle
Method and Device for Exchanging Data Using a Virtual Fifo Data Structure
Application:
12/279,952 →
Publication:
US 2008/0313363
Semiconductor Device Including a Coupled Dielectric Layer and Metal Layer, Method of Fabrication Thereof, and Passivating Coupling Material Comprising Multiple Organic Components for Use in a Semiconductor Device
Software Pipelining
Testing Non-Volatile Memory Devices for Charge Leakage
Integrated System for Semiconductor Substrate Processing Using Liquid Phase Metal Deposition
Application:
12/280,482 →
Publication:
US 2009/0301867
Device and Method for Testing a Device
Semiconductor Device Structure and Integrated Circuit Therefor
Method and Device for Processing Frames
Task Scheduling Method and Apparatus
Method and Device for Recognizing a Synchronization Message from a Wireless Telecommunication Device
Method and Apparatus for Enhanced Data Rate Adaptation and Lower Power Control in a Wlan Semiconductor Chip
Method and System for Tuning an Antenna
Bitline Current Generator for a Non-Volatile Memory Array and a Non-Volatile Memory Array
Non-Volatile Memory Device and a Programmable Voltage Reference for a Non-Volatile Memory Device
Wordline Driver for a Non-Volatile Memory Device, a Non-Volatile Memory Device and Method
Data Interleaver
Electronic Device and Integrated Circuit Comprising a Delta-Sigma Converter and Method Therefor
Apparatus for Detecting Clock Failure and Method Therefor
Apparatus and Method for Providing a Clock Signal
Power Amplifier with Pre-Distorter
Process for Filling Recessed Features in a Dielectric Substrate
Discharge Protection Apparatus and Method of Protecting an Electronic Device
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 1, 2012
From: FREESCALE SEMICONDUCTOR, INC
To: RYO HOLDINGS, LLC
Reel/Frame 028139/0475 →
Correction to the Assignee Name on the Recordation Cover Sheet of the Assignment Recorded at 014696/0149 on 6/04/2004. the Correct Assignee Name Is Motorola, Inc.
May 24, 2012
From: ZOSO, LUCIANO; CHIN, ALLAN P.; LESTER, DAVID P.
To: MOTOROLA, INC.
Reel/Frame 028275/0124 →
Release of Security Interest
Jun 7, 2012
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
Reel/Frame 028331/0948 →
Release of Security Interest
Jun 7, 2012
From: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 028331/0957 →
Assignment of Assignor's Interest
Jul 26, 2013
From: SIGMATEL, LLC
To: ACACIA RESEARCH GROUP
Reel/Frame 030887/0835 →
Assignment of Assignor's Interest
Aug 16, 2013
From: ACACIA RESEARCH GROUP LLC
To: PROGRESSIVE SEMICONDUCTOR SOLUTIONS LLC
Reel/Frame 031029/0762 →
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Security Agreement
Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
Assignment of Assignor's Interest
Sep 3, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033677/0920 →
Assignment of Assignor's Interest
Sep 3, 2014
From: SIGMATEL, L.L.C.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033677/0968 →
Assignment of Assignor's Interest
Sep 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033687/0336 →
Assignment of Assignor's Interest
Oct 21, 2014
From: SIGMATEL, L.L.C.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033996/0485 →
Assignment of Assignor's Interest
Oct 23, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZOZO MANAGEMENT, LLC
Reel/Frame 034038/0946 →
Assignment of Assignor's Interest
Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
Assignment of Assignor's Interest
Jan 7, 2015
From: ZOZO MANAGEMENT, LLC
To: APPLE INC.
Reel/Frame 034732/0019 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Assignment of Assignor's Interest
Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →