Dynamic address-type selection control in a data processing system
View Patent ↗A translated address and an untranslated address associated with a same processor operation are received. An address-type indicator is provided whose value is indicative of whether the translated or untranslated address is to be used for creating a debug message. The value of the address-type indicator is selectively modified in response to occurrence of one or more selected debug events. Based at least in part on the value of the address-type indicator, the translated or untranslated address is selected. The address-type indicator may be selectively overridden to select the translated or untranslated address as the selected address based on whether a process identifier is at least one of a set of process identifiers or whether at least one of the translated or untranslated address falls within one or more predetermined address ranges. A debug message is created using at least a portion of the selected address.
1. A method for generating a debug message in a data processing system, the method comprising:
receiving a translated address and an untranslated address associated with a same processor operation;
providing an address-type indicator whose value is indicative of whether the translated address or the untranslated address is to be used for creating a debug message;
selectively modifying the value of the address-type indicator in response to an occurrence of one or more selected debug events;
selecting, based at least in part on the value of the modified address-type indicator, the translated address or the untranslated address as a selected address, wherein selecting includes overriding the address type indicator with the modified address-type indicator and determining the value of the modified address-type indicator to select the translated address or the untranslated address as the selected address; and
creating a debug message using at least a portion of the selected address.
2. The method of claim 1 , further comprising:
providing debug event selection control information to indicate the one or more selected debug events.
3. The method of claim 2 , wherein the debug event selection control information further indicates how to selectively modify the value of the address-type indicator in response to the occurrence of the one or more selected debug events.
4. The method of claim 3 , wherein the selectively modifying the value of the address-type indicator comprises:
setting the address-type indicator to a first predetermined value when the debug event selection control information has a first value; and
setting the address-type indicator to a second predetermined value different from the first predetermined value when the debug event selection control information has a second value.
5. The method of claim 3 , wherein the selectively modifying the value of the address-type indicator comprises:
toggling the address-type indicator when the debug event selection control information has a first value.
6. The method of claim 1 , wherein the debug message is further characterized as a program trace debug message.
7. The method of claim 1 , wherein the selectively overriding the address-type indicator is performed based on whether a process identifier associated with the same processor operation is at least one of a set of process identifiers.
8. The method of claim 1 , wherein the selectively overriding the address-type indicator is preformed based on whether at least one of the translated address or the untranslated address falls within a predetermined address range.
9. The method of claim 1 , wherein the debug message is further characterized as a data trace debug message.
10. A method for generating a debug message in a data processing system, the method comprising:
receiving a translated address and an untranslated address associated with a same processor operation;
providing an address-type indicator which indicates whether the translated address or the untranslated address is to be used for creating a debug message;
selectively overriding the address-type indicator based on a process identifier associated with the same processor operation or based on whether at least one of the translated address or the untranslated address falls within one or more predetermined address ranges to select one of the translated address or the untranslated address as a selected address; and
creating a debug message using at least a portion of the selected address.
11. The method of claim 10 , wherein the selectively overriding comprises:
selectively overriding the address-type indicator based on whether the process identifier associated with the same processor operation is at least one of a set of process identifiers.
12. The method of claim 10 , wherein the one or more predetermined address ranges are user programmable.
13. The method of claim 10 , wherein the selectively overriding the address-type indicator based on whether the at least one of the translated address or the untranslated address falls within the one or more predetermined address ranges comprises:
when the translated address or the untranslated address falls within the one or more predetermined address ranges, selecting a first address from the translated address and the untranslated address as the selected address; and
when the translated address or the untranslated address falls outside the one or more predetermined address ranges, selecting a second address, different from the first address, from the translated address and the untranslated address as the selected address.
14. The method of claim 10 , wherein the debug message is further characterized as a program trace debug message.
15. A data processing system, comprising:
address translation logic which translates an untranslated address associated with a processor operation of the data processing system to a translated address associated with the processor operation;
storage circuitry which stores an address-type indicator whose value is indicative of whether the translated address or the untranslated address is to be used for creating a debug message;
modification circuitry which selectively modifies the value of the address-type indicator in the storage circuitry in response to an occurrence of one or more selected debug events;
selection circuitry which selects, based at least in part on the value of the address-type indicator, the untranslated address associated with the processor operation or the translated address associated with the processor operation as a selected address;
override logic which, based on whether a process identifier associated with the processor operation is at least one of a set of process identifiers, provides an override indicator to the selection circuitry, wherein the selection circuitry selects the selected address based on the value of the address-type indicator and the override indicator; and
debug message generation circuitry which generates a debug message corresponding to the processor operation using the selected address provided by the selection circuitry.
16. The data processing system of claim 15 , further comprising:
second storage circuitry, coupled to the modification circuitry, which stores debug event selection control information which indicates the one or more selected debug events and how to selectively modify the value of the address-type indicator in response to the occurrence of the one or more selected debug events.
17. The data processing system of claim 16 , wherein the modification circuitry sets the address-type indicator to a first predetermined value when the debug event selection control information has a first value, sets the address-type indicator to a second predetermined value when the debug event selection control information has a second value, and toggles the value of the address-type indicator when the debug event selection control information has a third value.
18. The data processing system of claim 16 , further comprising:
third storage circuitry, coupled to the modification circuitry, which indicates the occurrence of the one or more selected debug events.
19. The data processing system of claim 15 , further comprising:
override logic, which based on whether at least one of the translated address or the untranslated address falls within a predetermined address range, provides an override indicator to the selection circuitry, wherein the selection circuitry selects the selected address based on the value of the address-type indicator and the override indicator.