Processor and method for altering address translation
View Patent ↗In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.
1. A method for translating a logical address into a physical address comprising:
providing a processor having an address translation table;
providing a logical address to the address translation table;
providing a control signal in response to at least one of: (1) a predetermined system event, (2) a program counter of the processor matching a predetermined value or (3) at least one signal generated outside the processor;
when the control signal has a first value, providing a first physical address from the address translation table corresponding to the logical address; and
when the control signal has a second value, providing a second physical address from the address translation table, different from the first physical address, corresponding to the logical address, wherein the first physical address and the second physical address are stored in at least one valid entry of the address translation table.
2. The method of claim 1 , wherein the first physical address is stored in a first valid entry of the address translation table, the first valid entry having a tag field which matches the logical address and a valid field indicating the first valid entry is valid.
3. The method of claim 2 , wherein the second physical address is stored in a second valid entry of the address translation table, the second valid entry having a tag field which matches the logical address and a valid field indicating the second valid entry is valid.
4. The method of claim 2 , wherein the first physical address is stored in a first field of the first valid entry and the second physical address is stored in a second field of the first valid entry of the address translation table, and wherein providing the control signal comprises:
providing the control signal to select one of the first field or the second field of the first valid entry based on a value of the control signal.
5. The method of claim 1 , wherein the address translation table has a first portion storing the first physical address and a second portion storing the second physical address, and wherein providing the control signal comprises:
providing the control signal to activate one of the first portion or the second portion based on a value of the control signal.
6. The method of claim 1 , wherein the address translation table has a first portion storing the first physical address and a second portion storing the second physical address, and wherein providing the control signal comprises:
providing the control signal to select one of an output of the first portion or an output of the second portion based on a value of the control signal.
7. A method for translating a logical address into a physical address comprising:
providing a processor having an address translation table;
providing a logical address to the address translation table, wherein the address translation table includes:
a first entry having a tag field which matches the logical address, a physical address field storing a first physical address, and a valid field indicating that the first entry is valid, and
a second entry having a tag field which matches the logical address, a physical address field storing a second physical address, different from the first physical address, and a valid field indicating that the second entry is valid;
providing a control signal;
when the control signal has a first value, providing the first physical address; and
when the control signal has a second value, providing a second physical address.
8. The method of claim 7 , wherein the address translation table has a first portion storing the first physical address and a second portion storing the second physical address, and wherein providing the control signal comprises:
providing the control signal to activate one of the first portion or the second portion based on a value of the control signal.
9. The method of claim 7 , wherein the address translation table has a first portion storing the first physical address and a second portion storing the second physical address, and wherein providing the control signal comprises:
providing the control signal to select one of an output of the first portion or an output of the second portion based on a value of the control signal.
10. The method of claim 7 , wherein providing the control signal comprises:
providing the control signal in response to at least one selected from a group consisting of:
an external signal generated outside the processor,
a program counter of the processor matching a predetermined value, and
a predetermined system event.
11. A processor, comprising:
an address translation table having an input for receiving a logical address, a first entry comprising a tag field for storing a tag value which matches the logical address, a first physical address field for storing a first physical address and a valid field for indicating that the first entry is valid, and a second entry comprising a tag field for storing the tag value which matches the logical address, a second physical address field for storing a second physical address that is different from the first physical address and a valid field indicating the second entry is valid; and
control circuitry coupled to the address translation table, the control circuitry providing a control signal, the address translation table providing the first physical address when the control signal has a first value and providing the second physical address when the control signal has a second value.
12. The processor of claim 11 , wherein the first physical address is stored in a first field of the first valid entry and the second physical address is stored in a second field of the first valid entry, each of the first and second physical addresses corresponding to the tag field of the first valid entry.
13. The processor of claim 12 , wherein the address translation table has a second valid entry, the second valid entry having a tag field and physically storing a single physical address corresponding to the tag field.
14. The processor of claim 11 , wherein the control circuitry is responsive to at least one external signal generated outside the processor.
15. The processor of claim 11 , wherein the control circuitry is responsive to a match indicator provided when a program counter of the processor matches a predetermined value.
16. The processor of claim 11 , wherein the control circuitry is responsive to a predetermined system event.