IP Library Granted Patent US 7,930,522
Granted Patent B2
US 7,930,522 · App. 12/194,279 · Granted Apr 19, 2011

Method for speculative execution of instructions and a device having speculative execution capabilities

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,930,522
App. No.
12/194,279
Granted
Apr 19, 2011
Kind
B2
Abstract

A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

Claims (33)

1. A method for speculative execution of instructions, the method comprising: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

2. The method according to claim 1 comprising ignoring an outcome of an execution of at least one conditional instruction if the resolution of the compare instruction indicates that a condition associated with the at least one conditional instruction was not fulfilled.

3. The method according to claim 1 wherein the speculatively executing comprises executing a conditional instruction that depends upon an outcome of another conditional instruction that is decoded during the speculation window.

4. The method according to claim 1 wherein the speculatively executing comprises:

executing a first conditional instruction that replaces an old value of a certain register by a new value; and

executing a second conditional instruction that uses the new value of the register if the first and second conditional instructions have the same dependency on the resolution of the compare instruction.

5. The method according to claim 1 wherein the speculatively execution comprises:

executing a first conditional instruction that replaces an old value of a certain register by a new value; and

executing a second conditional instruction that uses the old value of the register if the first and second conditional instructions have opposing dependencies on the resolution of the compare instruction.

6. The method according to claim 1 comprising executing, in parallel, conditional instructions that have opposing dependencies on the resolution of the compare instruction and selecting, in response to a resolution of the compare instruction, an outcome of one conditional instruction out of the conditional instructions.

7. The method according to claim 1 comprising updating status data that indicates which registers are affected by the non-conditional instructions and indicates registers are affected by the conditional instructions.

8. The method according to claim 1 wherein the speculatively executing comprises forwarding values of registers affected by the conditional instructions during the speculation window.

9. The method according to claim 1 wherein the conditional instructions are part of very long instruction words.

10. The method according to claim 1 wherein the conditional instructions are selected from a group consisting of load store instructions and pointer arithmetic instructions.

11. A device having speculative execution capabilities, the device comprises:

a first sequence of pipelined stages that is configured to execute a compare instruction; wherein the pipelined stages comprises a decoding stage, multiple intermediate pipeline stages and an execution stage;

a speculative execution module that is configured to:

speculatively execute, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and

stall an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

12. The device according to claim 11 comprising wherein the device ignores an outcome of an execution of at least one conditional instruction if the resolution of the compare instruction indicates that a condition associated with the at least one conditional instruction was not fulfilled.

13. The device according to claim 11 wherein the speculative execution module is configured to executing a conditional instruction that depends upon an outcome of another conditional instruction that is decoded during the speculation window.

14. The device according to claim 11 wherein speculative execution module is configured to:

execute a first conditional instruction that replaces an old value of a certain register by a new value; and

execute a second conditional instruction that uses the new value of the register if the first and second conditional instructions have the same dependency on the resolution of the compare instruction.

15. The device according to claim 11 wherein the speculative execution module is configured to:

execute a first conditional instruction that replaces an old value of a certain register by a new value; and

execute a second conditional instruction that uses the old value of the register if the first and second conditional instructions have opposing dependencies on the resolution of the compare instruction.

16. The device according to claim 11 comprising multiple speculative execution modules that are configured to execute, in parallel, conditional instructions that have opposing dependencies on the resolution of the compare instruction; and

wherein the device is configured to select, in response to a resolution of the compare instruction, an outcome of one conditional instruction out of the conditional instructions.

17. The device according to claim 11 wherein the speculative execution module is configured to update status data that indicates which registers are affected by the non-conditional instructions and indicates registers that are affected by the conditional instructions.

18. The device according to claim 11 wherein the speculative execution module is configured to forward values of registers affected by the conditional instructions during the speculation window.

19. The device according to claim 11 wherein the device comprises multiple sequences of pipelined stages and at least one speculative execution module for executing very long instruction words.

20. The device according to claim 11 wherein the conditional instructions are selected from a group consisting of load store instructions and pointer arithmetic instructions.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2010
From: SHMUELI, GUY; BARAK, ITZHAK; DAYAN, URI; PARAN, AMIR; ROZENBERG, IDAN; SCHUPPER, DORON
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 024014/0520 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →