Data conversion circuitry having successive approximation circuitry and method therefor
View Patent ↗A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.
1. A method, comprising:
performing a partial single-ended approximation of an analog-to-digital converter minus input using a first DAC and a first comparator to produce a minus result;
performing a full single-ended approximation of an analog-to-digital converter plus input using a second DAC and a second comparator to produce a plus result, wherein the step of performing the partial single-ended approximation of the analog-to-digital converter minus input causes a negative input to the second comparator to be within a predetermined range of a common mode voltage; and
combining the minus result and the plus result to produce a conversion result.
2. A method as in claim 1 , further comprising:
providing a differential bias capacitor having a first terminal coupled to a reference voltage and having a second terminal coupled to a positive input of the second comparator.
3. A method as in claim 2 , wherein the differential bias capacitor has a capacitance approximately equal to a capacitance of a predetermined capacitor in the first DAC.
4. A method as in claim 2 , wherein the reference voltage is a high reference voltage during at least a portion of the step of performing the partial single-ended approximation of the analog-to-digital converter minus input.
5. A method as in claim 4 , further comprising:
selectively coupling the first terminal of the differential bias capacitor to a low reference voltage depending upon an output of the second comparator.
6. A method as in claim 5 , wherein the step of selectively coupling comprises:
coupling the first terminal of the differential bias capacitor to the low reference voltage when the output of the second comparator is high.
7. A method as in claim 1 , wherein a negative input of the first comparator is coupled to a common mode voltage.
8. A method as in claim 1 , wherein the second comparator has greater accuracy than the first comparator.
9. A data converter, comprising:
first circuitry which performs a partial single-ended approximation of an analog-to-digital converter minus input to produce a minus result, wherein the first circuitry comprises:
a first DAC having a first input for receiving the analog-to-digital converter minus input, having a second input for receiving a first reference voltage, and having an output; and
a first comparator having a first input coupled to the output of the first DAC, having a second input coupled to a common mode voltage, and having an output for serially providing the minus result;
second circuitry which performs a full single-ended approximation of an analog-to-digital converter plus input to produce a plus result, wherein the second circuitry comprises:
a second DAC having a first input for receiving the analog-to-digital converter plus input, having a second input for receiving a second reference voltage, and having an output; and
a second comparator having a first input coupled to the output of the second DAC, having a second input coupled to the output of the first DAC, and having an output for serially providing the plus result; and
result circuitry which combines the minus result and the plus result to produce a conversion result.
10. A data converter as in claim 9 , further comprising:
a differential bias capacitor having a first terminal coupled to a third reference voltage and having a second terminal coupled to the first input of the second comparator.
11. A data converter as in claim 10 , wherein the differential bias capacitor has a capacitance approximately equal to a capacitance of a predetermined capacitor in the first DAC.
12. A data converter as in claim 9 , wherein the result circuitry comprises:
computation circuitry for determining a difference between the plus result and the minus result to produce a differential result.
13. A data converter as in claim 12 , wherein the computation circuitry subtracts the minus result from the plus result to produce the differential result.
14. A data converter as in claim 13 , wherein the computation circuitry subtracts a predetermined amount from the differential result to produce the conversion result when a first terminal of a bias capacitor was switched from a first reference voltage to a second reference voltage during conversion.
15. A method, comprising:
performing a partial successive approximation routine in an analog-to-digital converter to produce a first result, wherein the step of performing the partial successive approximation routine comprises:
providing a voltage at a negative input of a comparator, wherein the voltage is substantially equal to a common mode voltage of the comparator;
after said step of performing the partial successive approximation routine, selectively switching a differential bias capacitor from a first reference voltage to a second reference voltage when a positive input of the comparator is higher than the negative input of the comparator;
after said step of performing the partial successive approximation routine, performing a full successive approximation routine in the analog-to-digital converter to produce a second result;
combining the minus result and the plus result to produce a differential result; and
subtracting a predetermined value from the differential result to produce a conversion result if the differential bias capacitor was switched from the first reference voltage to the second reference voltage during said step of selectively switching.
16. A method as in claim 15 , further comprising:
providing a first comparator in the analog-to-digital converter, the first comparator having a first accuracy; and
providing a second comparator in the analog-to-digital converter, the second comparator having a second accuracy,
wherein the second accuracy of the second comparator is at least twice as accurate as the first accuracy of the first comparator.
17. A method as in claim 16 , wherein the first comparator is used to perform said step of performing the partial successive approximation routine, and wherein the second comparator is used to perform said step of performing the full successive approximation routine.