IP Library Granted Patent US 8,364,896
Granted Patent B2
US 8,364,896 · App. 12/234,618 · Granted Jan 29, 2013

Method and apparatus for configuring a unified cache based on an associated error rate

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Quick Facts
Patent No.
US 8,364,896
App. No.
12/234,618
Granted
Jan 29, 2013
Kind
B2
Abstract

A method of configuring a unified cache includes identifying unified cache way assignment combinations for an application unit. Each combination has an associated error rate. A combination is selected based at least in part on the associated error rate. The unified cache is configured in accordance with the selected combination for execution of the application-unit.

Claims (25)

1. A method of configuring a unified cache, comprising:

(a) identifying unified cache way assignment combinations for an application unit, wherein each combination has an associated error rate;

(b) selecting a selected combination based at least in part on the associated error rate, wherein the associated error rate is exclusive of cache misses; and

(c) configuring the unified cache in accordance with the selected combination for execution of the application unit, wherein the unified cache is an n-way set associative unified cache, and each way is configurable for one of the following allocations at a time: exclusively for data-type information, exclusively for instruction-type information. and both data-type and instruction-type information.

2. The method of claim 1 wherein (b) comprises selecting any combination having an associated error rate that does not exceed the associated error rate of any other combination of the unified cache way assignment combinations.

3. The method of claim 1 wherein (b) comprises selecting any combination having an associated error rate that does not exceed a pre-determined threshold, ε T .

4. The method of claim 1 wherein error management of a way is selected in accordance with an information type for which the way is allocated.

5. The method of claim 4 wherein error correction code error management is used for any way allocated exclusively for instruction-type information.

6. The method of claim 5 wherein parity error detection code error management is utilized for any way allocated exclusively for data-type information.

7. A method of configuring a unified cache, comprising:

(a) identifying unified cache way assignment combinations for an application unit, wherein each combination has an associated error rate and an associated performance rating;

(b) selecting a selected combination based on both the associated error rate and the associated performance rating, wherein the associated error rate is exclusive of cache misses; and

(c) configuring the unified cache in accordance with the selected combination for execution of the application unit, wherein the unified cache is an n-way set associative unified cache, and each way is configurable for one of the following allocations at a time: exclusively for data-type information, exclusively for instruction-type information, and both data-type and instruction-type information

8. The method of claim 7 wherein (b) comprises eliminating any combination having an associated error rate that exceeds a pre-determined threshold, ε T as a candidate for the selected combination.

9. The method of claim 7 wherein (b) comprises selecting a combination having a highest performance rating from a subset of combinations having an associated error rate that does not exceed a pre-determined threshold, ε T .

10. The method of claim 7 wherein (b) comprises selecting a combination from the subset of combinations having an associated error rate that does not exceed a pre-determined threshold, ε T , wherein the selected combination has a performance rating no less than the performance rating of any other combination of the subset of combinations.

11. The method of claim 7 wherein (b) comprises selecting a combination from the subset of combinations having an associated performance rating that is not less than a pre- determined threshold, P T , wherein the selected combination has an error rate no greater than the error rate of any other combination of the subset of combinations.

12. The method of claim 7 wherein error management of a way is selected in accordance with an information type for which the way is allocated.

13. The method of claim 12 wherein error correction code error management is used for any way allocated exclusively for instruction-type information.

14. The method of claim 12 wherein parity error detection code error management is utilized for any way allocated exclusively for data-type information.

15. A method of configuring a unified cache, comprising:

(a) identifying unified cache way assignment combinations for an application unit, wherein each combination has an associated error rate and an associated performance rating;

(b) selecting a selected combination based on both the associated error rate and the associated performance rating, wherein the selected combination is selected in accordance with one of a first constraint and a second constraint, wherein in accordance with the first constraint the selected combination is selected from a subset of combinations with error rates that do not exceed a pre-determined error threshold, ε T and the selected combination has a performance rating no less than the performance rating of any other combination of the subset, wherein in accordance with the second constraint the selected combination is selected from a subset of combinations with performance ratings that are not less than a pre-determined performance threshold, P T , wherein the associated error rate of the selected combination is no greater than the error rate of any other combination of the subset; and

(c) configuring the unified cache in accordance with the selected combination for execution of the application unit.

16. The method of claim 15 wherein each way is configurable for one of the following allocations at a time: exclusively for data-type information, exclusively for instruction-type information, and both data-type and instruction-type information.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2008
From: MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 021560/0384 →