IP Library Patent Application 12195225
Patent Application
App. No. 12/195,225

DEBUG INSTRUCTION FOR USE IN A MULTI-THREADED DATA PROCESSING SYSTEM

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Quick Facts
Patent No.
US None
App. No.
12/195,225
Abstract

For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread.

Claims (23)

1 . In a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method comprising:

in response to execution of a debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread.

2 . The method of claim 1 , wherein generating the debug event further comprises posting a debug event to a debug event register.

3 . The method of claim 2 , wherein generating the debug event further comprises posting the debug event to the debug event register even when the second thread is not halted.

4 . The method of claim 1 , wherein generating the debug event further comprises determining whether an external debugger is enabled.

5 . The method of claim 4 further comprising processing an instruction exception when the external debugger is not enabled.

6 . The method of claim 1 further comprising generating a debug interrupt corresponding to the second thread when interrupts are enabled.

7 . The method of claim 1 , wherein the second thread is selected from a group consisting of a plurality of threads and wherein the second thread is selected based on a thread select field in the debug instruction.

8 . The method of claim 7 , wherein when the thread select field has a predetermined value, the second thread is selected based on a value stored in a thread key register.

9 . The method of claim 2 , wherein when the debug event is posted to the debug event register, if the second thread is inactive, the second thread receives a debug interrupt when the second thread becomes active.

10 . The method of claim 1 , wherein the processor is further configured to execute a third set of instructions corresponding to a third thread, and wherein the method further comprises in response to the execution of the debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by each of the second thread and the third thread.

11 . In a data processing system comprising a processor configured to overlap execution of a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method comprising:

in response to execution of a debug instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein the second thread is selected from a group consisting of a plurality of threads and wherein the second thread is selected based on a thread select field.

12 . The method of claim 11 , wherein generating the debug event further comprises posting a debug event to a debug event register.

13 . The method of claim 12 , wherein generating the debug event further comprises posting the debug event to the debug event register even when the second thread is not halted.

14 . The method of claim 11 , wherein generating the debug event further comprises determining whether an external debugger is enabled.

15 . The method of claim 14 further comprising generating an instruction exception when the external debugger is not enabled.

16 . The method of claim 11 further comprising processing a debug interrupt corresponding to the second thread when interrupts are enabled.

17 . The method of claim 11 , wherein the thread select field comprises at least a portion of the debug instruction encoding and wherein when the thread select field has a predetermined value, the second thread is selected based on a value stored in a thread key register.

18 . A data processing system comprising:

a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, the processor further configured, in response to execution of a debug instruction by the first thread while executing the first set of instructions, to generate a debug event for processing by the second thread.

19 . The data processing system of claim 18 , wherein the processor further comprises thread control circuitry configured to post a debug event to a debug event register.

20 . The data processing system of claim 18 , wherein the second thread is selected from a group consisting of a plurality of threads and wherein the second thread is selected based on a thread select field in the debug instruction.

Assignments (5)
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2008
From: MOYER, WILLIAM C.; SNYDER, MICHAEL D.; WHISENHUNT, GARY L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 021429/0194 →