IP Library Granted Patent US 7,397,001
Granted Patent B2
US 7,397,001 · App. 11/676,810 · Granted Jul 8, 2008

Multi-strand substrate for ball-grid array assemblies and method

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,397,001
App. No.
11/676,810
Granted
Jul 8, 2008
Kind
B2
Abstract

A multi-strand printed circuit board substrate for ball-grid array (BGA) assemblies includes a printed wiring board ( 11 ) having a plurality of BGA substrates ( 12 ) arranged in N rows ( 14 ) and M columns ( 16 ) to form an N by M array. N and M are greater than or equal to 2 and the size of the N by M array is selected such that each of the plurality of BGA substrates ( 12 ) maintains a planarity variation less than approximately 0.15 mm (approximately 6 mils). The printed wiring board ( 11 ) has a thickness ( 26 ) sufficient to minimize planarity variation and to allow a manufacturer to use automated assembly equipment without having to use support pallets or trays.

Claims (27)

1. A method for assembling ball-grid array (BGA) packages, comprising the steps of:

providing a plurality of BGA substrates arranged in an N by M array within a printed circuit board having a thickness, wherein N and M are greater than or equal to 2, each BGA substrate having a plurality of bond posts and a plurality of contact pads;

attaching a semiconductor die to each of the plurality of BGA substrates, wherein each BGA substrate corresponds to an attached semiconductor die, each semiconductor die having a plurality of bond pads;

encapsulating the semiconductor die with an encapsulant;

curing the encapsulant; and

dividing the N by M array into separate BGA packages, wherein the size of the N by M array and the thickness of the printed circuit board are such that each of the plurality of BGA substrates maintains a planarity variation less than approximately 0.15 mm after assembly.

2. The method of claim 1 , wherein each of the plurality of BGA substrates corresponds to an individual device.

3. The method of claim 1 , wherein each of one of BGA substrates within the plurality of BGA substrates has a corresponding individual device within a plurality of individual devices.

4. The method of claim 1 , wherein the step of attaching comprises attaching a first die to a first one of the plurality of BGA substrates and attaching a second die to a second one of the plurality of BGA substrates.

5. The method of claim 1 , wherein the step of encapsulating the semiconductor die includes encapsulating with an encapsulant having a thermal coefficient of expansion close to that of the printed circuit board.

6. The method of claim 1 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a plurality of stress-relief slots at various locations within the printed circuit board.

7. The method of claim 1 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a thickness greater than approximately 0.5 mm.

8. The method of claim 1 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a width on an order of 63 mm.

9. The method of claim 1 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a length in a range from approximately 187 mm to 12 mm.

10. The method of claim 1 , wherein the at least one bond pad comprises copper or gold plated copper.

11. The method of claim 2 , wherein each of the individual devices comprises a semiconductor die.

12. The method of claim 6 , wherein at least one of the plurality of stress-relief slots is of a different size from another of the plurality of stress-relief slots.

13. The method of claim 10 , wherein the at least one bond pad is one of a solid metallization area or a patterned metallization area having a specific geometric shape, wherein the specific geometric shape is a cross or Union Jack.

14. The method of claim 2 , wherein the step of attaching comprises attaching a first die to a first one of the plurality of BGA substrates and attaching a second die to a second one of the plurality of BGA substrates.

15. The method of claim 14 , wherein the step of encapsulating the semiconductor die includes encapsulating with an encapsulant having a thermal coefficient of expansion close to that of the printed circuit board.

16. The method of claim 15 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a plurality of stress-relief slots at various locations within the printed circuit board.

17. The method of claim 16 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a thickness greater than approximately 0.5 mm.

18. The method of claim 17 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a width on an order of 63 mm.

19. The method of claim 18 , wherein the step of providing the plurality of BGA substrates arranged in the N by M array within the printed circuit board includes providing the plurality of BGA substrates within the printed circuit board having a length in a range from approximately 187 mm to 12 mm.

20. The method of claim 16 , wherein at least one of the plurality of stress-relief slots is of a different size from another of the plurality of stress-relief slots.

21. The method of claim 20 , wherein the at least one bond pad comprises copper or gold plated copper.

22. The method of claim 21 , wherein the at least one bond pad is one of a solid metallization area or a patterned metallization area having a specific geometric shape, wherein the specific geometric shape is a cross or Union Jack.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0640 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0757 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Dec 9, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021936/0772 →
SECURITY AGREEMENT Recorded Sep 19, 2007
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 019847/0804 →