Device and method for evaluating electrostatic discharge protection capabilities
View Patent ↗A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.
1. A method for evaluating ESD protection capabilities of an integrated circuit, the method comprises:
connecting multiple test probe to multiple integrated circuit testing points;
charging a discharge capacitor to an ESD protection circuit triggering voltage level;
coupling the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit;
measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and
determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal.
2. The method according to claim 1 wherein the charging is preceded by defining the ESD protection circuit triggering voltage level.
3. The method according to claim 1 wherein the defining is responsive to a discharge period of the discharge capacitor and to a predefined high repetition rate.
4. The method according to claim 1 wherein the coupling comprises selecting a test path between the discharge capacitor and the integrated circuit out of multiple test paths defined between the discharge capacitor and the integrated circuit.
5. The method according to claim 1 wherein the coupling comprises coupling the discharge capacitor to the integrated circuit during a testing period that is longer than three oscillation cycles of an oscillatory circuit that comprises the discharge capacitor and at least a portion of the integrated circuit.
6. The method according to claim 1 wherein the charging comprises charging the discharge capacitor to a voltage level that is lower than 200 v.
7. The method according to claim 1 wherein the charging comprises charging the discharge capacitor to a voltage level that is lower than 100 v.
8. The method according to claim 1 wherein the charging comprises charging the discharge capacitor to a voltage level that is lower than 60 v.
9. The method according to claim 1 wherein the determining comprises comparing an estimated response of an integrated circuit that comprises a functional ESD protection circuit to the at least one signal.
10. The method according to claim 1 wherein the determining comprises finding a match between a response pattern corresponding to the at least one measured signal and one out of multiple response patterns that characterize different ESD protection mechanisms.
11. A device for evaluating ESD protection capabilities of an integrated circuit, the device comprises:
multiple test probes adapted to be connected to multiple integrated circuit testing point; a discharge capacitor;
a charging circuit adapted to charge the capacitor to an ESD protection circuit triggering voltage level;
a discharging circuit, adapted to selectively couple the discharge capacitor, during a testing period, to the integrated circuit such that the discharge capacitor interacts with the integrated circuit while being discharged;
a controller; for controlling said discharging circuit and said charging circuit; and
a processor, coupled to the multiple test probes, wherein the processor is adapted to process multiple signals received from the multiple test probes and to assist in determining at least one ESD protection characteristic of the integrated circuit.
12. The device according to claim 11 wherein the device is adapted to define the ESD protection circuit triggering voltage level.
13. The device according to claim 11 wherein the device defines the ESD protection circuit triggering voltage level in response to a discharge period of the discharge capacitor and to a predefined high repetition rate.
14. The device according to claim 11 wherein the discharging circuit comprises multiple test paths and wherein the device selects between the multiple test paths defined between the discharge capacitor and the integrated circuit.
15. The device according to claim 11 wherein the testing period that is longer than three oscillation cycles of an oscillatory circuit that comprises the discharge capacitor and at least a portion of the integrated circuit.
16. The device according to claim 11 wherein the charging circuit is adapted to charge the discharge capacitor to a voltage level that is lower than 200 v.
17. The device according to claim 11 wherein the charging circuit is adapted to charge the discharge capacitor to a voltage level that is lower than 100 v.
18. The device according to claim 11 wherein the charging circuit is adapted to charge the discharge capacitor to a voltage level that is lower than 60 v.
19. The device according to claim 11 wherein the processor is adapted to compare an estimated response of an integrated circuit that comprises a functional ESD protection circuit to the at least one signal.
20. The device according to claim 11 wherein the processor is adapted to find a match between a response pattern corresponding to the at least one measured signal and one out of multiple response patterns that characterize different ESD protection mechanisms.