IP Library Granted Patent US 7,393,752
Granted Patent B2
US 7,393,752 · App. 11/189,587 · Granted Jul 1, 2008

Semiconductor devices and method of fabrication

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Quick Facts
Patent No.
US 7,393,752
App. No.
11/189,587
Granted
Jul 1, 2008
Kind
B2
Abstract

A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (<0.3 μm) power MOSFET using existing 0.13 μm process flow without additional masks and processing steps.

Claims (27)

1. A method of fabricating a semiconductor device including a semiconductor substrate having an epitaxial layer doped with a first type of doping material, the method comprising the steps of:

impurity doping a first region with the first type of doping material in said substrate to form a first doped well on a source side of the substrate;

forming a gate electrode overlying a surface of the substrate and having a gate dielectric formed therebetween;

forming a halo implant region on the source side of said substrate by depositing photoresist over a drain side of the substrate and implanting an impurity ion of the first type of doping material selectively into said first doped well at an angle greater than zero from an axis perpendicular to said surface of said silicon substrate, said impurity ion forming the halo implant region in self alignment with said gate electrode and on the source side of said substrate;

impurity doping a second region on a drain side of said substrate with a second type of doping material to form a lightly doped drain implant in self alignment with said gate electrode on the drain side of said substrate, wherein impurity doping the second region is performed with a photoresist over the source side of said substrate;

impurity doping a third region in said halo implant region to form a source region; and

impurity doping a fourth region in said lightly doped drain implant to form a drain region, wherein the halo implant region and the lightly doped drain implant extend beyond the source region and the drain region and into a channel area between the source region and the drain region.

2. The method of claim 1 , wherein the step of impurity doping a first region in said substrate comprises the step of implanting ions that comprise a material selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B).

3. The method of claim 1 , wherein the step of forming the halo implant region comprises the step of implanting impurity ions that comprise a material selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B).

4. The method of claim 1 , wherein the step of impurity doping a first region in said substrate to form a first doped well comprises the step of implanting boron at an implant concentration of 1×10 15 /cm 3 .

5. The method of claim 1 , further comprising the step of impurity doping a region within a portion of said first doped well to form a second doped well by chain implanting boron at energy of 15K to 500 KeV and at an implant concentration in a range of 1×10 17 /cm 3 to 2×10 18 /cm 3 .

6. The method of claim 1 , wherein the step of forming the halo implant region comprises the step of implanting boron at an energy of 30 KeV and at an implant concentration in a range of 5×10 18 /cm 3 to 6×10 18 /cm 3 .

7. The method of claim 1 , wherein the step of impurity doping a second region to form a lightly doped drain implant comprises the step of implanting boron at an energy of 30 KeV and at an implant concentration in a range of 1×10 18 /cm 3 to 5×10 18 /cm 3 .

8. A method of fabricating a semiconductor device including a semiconductor substrate, the method comprising the steps of:

depositing a first type of doping material to form a doped epitaxial layer on said surface of said substrate;

implanting a first impurity doped region in said doped epitaxial layer to form a doped well of the first type of doping material on a source side of said substrate;

forming a gate electrode overlying a surface of the substrate and having a gate dielectric formed therebetween;

forming a halo implant region on the source side of said substrate by depositing photoresist over a drain side of the substrate and implanting an impurity ion of the first type of doping material selectively into said doped well at an angle greater than zero from an axis perpendicular to said surface of said silicon substrate, said impurity ion forming the halo implant region in self alignment with said gate electrode and on the source side of said substrate;

implanting a second impurity doped region in said doped epitaxial layer on a drain side of said substrate to form a lightly doped drain implant of a second type of doping material in self alignment with said gate electrode on the drain side of said substrate, wherein implanting the second impurity doped region is performed with a photoresist over the source side of said substrate;

forming an insulating spacer about said gate electrode;

implanting a source region in said halo implant region; and

implanting a drain region in said lightly doped drain implant, wherein the halo implant region and the lightly doped drain implant extend beyond the source region and the drain region and into a channel area between the source region and the drain region.

9. The method of claim 8 , wherein the step of implanting forming a halo implant region comprises the step of implanting ions that comprise a material selected from the group consisting of germanium (Ge), arsenic (As), phosphorous (P), and boron (B).

10. The method of claim 8 , wherein the step of depositing a first type of doping material to form a doped epitaxial layer comprises the step of depositing boron at a concentration of 2×10 14 to 2×10 15 /cm.

11. The method of claim 8 , wherein the step of implanting a first impurity doped region in said doped epitaxial layer to form a doped well comprises the step of implanting boron at an energy of 30 KeV and at an implant concentration in a range of 1×10 17 /cm 3 to 2×10 18 /cm 3 .

12. The method of claim 8 , wherein the step of forming a halo implant region comprises the step of implanting boron at an energy of 30 KeV and at an implant concentration in a range of 5×10 18 /cm 3 to 6×10 18 /cm 3 .

13. The method of claim 8 , wherein the step of implanting a second impurity doped region in said doped epitaxial layer to form a lightly doped drain implant comprises the step of implanting boron at an energy of 30 KeV and at an implant concentration in a range of 1×10 18 /cm 3 to 5×10 18 /cm 3 .

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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