Electronic device including a transistor structure having an active region adjacent to a stressor layer
View Patent ↗An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
1. An electronic device comprising:
a first transistor structure of a first conductivity type including a first active region having a first edge that extends substantially along a first channel length direction;
a second transistor structure of the first conductive type including a second active region having a first edge that extends substantially along a second channel length direction;
a portion of a field isolation region lying between the first and second active regions; and
a first portion of a first layer of a first stress type overlying the portion of the field isolation region, wherein:
the first portion of the first layer is not a sidewall spacer;
the first portion of the first layer has a first edge and a second edge opposite the first edge;
the first edge of the first portion of the first layer lies closer to the first edge of the first active region as compared to the first edge of the second active region; and
the second edge of the first portion of the first layer lies closer to the first edge of the second active region as compared to the first edge of the first active region.
2. The electronic device of claim 1 , wherein the first transistor structure comprises a p-channel transistor structure, and the first stress type is compressive.
3. The electronic device of claim 2 , wherein each of the first and second active regions comprises a primary surface lying on a (100) or (110) crystal plane and oriented substantially in a direction of form <110>.
4. The electronic device of claim 1 , wherein:
the first active region comprises a channel width;
the first active region underlies the first portion of the first layer, wherein from a top view, the first portion of the first layer has a dimension that is measured in a direction substantially parallel to the channel width; and
the dimension is no greater than approximately a sum of the channel width and one unit of misalignment tolerance for a mask used to define the opening within the first layer.
5. The electronic device of claim 1 , wherein the first transistor structure comprises an n-channel transistor structure, and the first stress type is tensile.
6. The electronic device of claim 5 , wherein each of the first and second active regions comprises a primary surface lying on a (100) or (110) crystal plane and oriented substantially in a direction of form <100> or <110>.
7. The electronic device of claim 1 , wherein:
the first active region further comprises a second edge, a third edge, and a fourth edge, wherein from a top view, the first and second edges of the first active region lie along a first pair of opposite edges of the first active region, and the third and fourth edges of the first active region lie along a second pair of opposite edges of the first active region; and
the first portion of the first layer further comprises a third edge, and a fourth edge, wherein from the top view:
the second edge of the first portion of the first layer lies adjacent to the second edge of the first active region;
the third edge of the first portion of the first layer lies adjacent to the third edge of the first active region;
the fourth edge of the first portion of the first layer lies adjacent to the fourth edge of the first active region;
a first distance is a distance between the first edge of the first active region and the first edge of the first portion of the first layer;
a second distance is a distance between the second edge of the first active region and the second edge of the first portion of the first layer;
a third distance is a distance between the third edge of the first active region and the third edge of the first portion of the first layer;
a fourth distance is a distance between the fourth edge of the fourth active region and the fourth edge of the first portion of the first layer;
a first sum is a sum of the first and second distances, and a second sum is a sum of the third and fourth distances; and
the first sum is less than the second sum.
8. The electronic device of claim 1 , further comprising a second portion of the first layer overlying the portion of the field isolation region and the second active region, wherein the first and second portions of the first layer are separate and spaced apart from one another.
9. The electronic device of claim 8 , wherein from a top view, some, but not all, of the portion of the field isolation region lies between the first and second portions of the first layer.
10. The electronic device of claim 8 , wherein each of the first and second active regions comprises a primary surface lying on a (100) or (110) crystal plane and oriented substantially in a direction of form <100>.
11. The electronic device of claim 8 , wherein:
the second portion of the first layer has a first edge and a second edge opposite the first edge;
the first edge of the second portion of the first layer lies closer to the first edge of the second active region as compared to the first edge of the first active region; and
the second edge of the second portion of the first layer lies closer to the second edge of the second active region as compared to the first edge of the second active region.
12. The electronic device of claim 8 , wherein:
the first active region further comprises a second edge, a third edge, and a fourth edge, wherein from a top view, the first and second edges of the first active region lie along a first pair of opposite edges of the first active region, and the third and fourth edges of the first active region lie along a second pair of opposite edges of the first active region; and
the first portion of the first layer further comprises a third edge and a fourth edge, wherein from the top view:
the second edge of the first portion of the first layer lies adjacent to the second edge of the first active region;
the third edge of the first portion of the first layer lies adjacent to the third edge of the first active region;
the fourth edge of the first portion of the first layer lies adjacent to the fourth edge of the first active region;
a first distance is a distance between the first edge of the first active region and the first edge of the first portion of the first layer;
a second distance is a distance between the second edge of the first active region and the second edge of the first portion of the first layer;
a third distance is a distance between the third edge of the first active region and the third edge of the first portion of the first layer;
a fourth distance is a distance between the fourth edge of the fourth active region and the fourth edge of the first portion of the first layer;
a first sum is a sum of the first and second distances, and a second sum is a sum of the third and fourth distances; and
the first sum is less than the second sum.
13. The electronic device of claim 12 , wherein:
the second active region further comprises a second edge, a third edge, and a fourth edge, wherein from the top view, the first and second edges of the second active region lie along a first pair of opposite edges of the second active region, and the third and fourth edges of the second active region lie along a second pair of opposite edges of the second active region; and
the second portion of the first layer further comprises a third edge and a fourth edge, wherein from the top view:
the second edge of the second portion of the first layer lies adjacent to the second edge of the second active region;
the third edge of the second portion of the first layer lies adjacent to the third edge of the second active region;
the fourth edge of the second portion of the first layer lies adjacent to the fourth edge of the second active region;
a fifth distance is a distance between the first edge of the second active region and the first edge of the second portion of the first layer;
a sixth distance is a distance between the second edge of the second active region and the second edge of the second portion of the first layer;
a seventh distance is a distance between the third edge of the second active region and the third edge of the second portion of the first layer;
an eighth distance is a distance between the fourth edge of the second active region and the fourth edge of the second portion of the first layer;
a third sum is a sum of the fifth and sixth distances, and a fourth sum is a sum of the seventh and eighth distances; and
the third sum is less than the fourth sum.
14. The electronic device of claim 1 , further comprising:
a third transistor structure of a second conductivity type opposite the first conductivity type, wherein the third transistor structure includes a third active region having a first edge that extends substantially along a third channel length direction; and
a second layer of a second stress type opposite the first stress type, wherein the second layer overlies the third active region and is not a sidewall spacer.
15. The electronic device of claim 14 , wherein the second layer overlies substantially all of the third active region.
16. The electronic device of claim 15 , wherein the second layer overlies the portion of the field isolation region.
17. The electronic device of claim 14 , wherein:
the first and second transistor structures comprise p-channel transistor structures;
the third transistor structure comprises an n-channel transistor structure;
the first stress type is compressive; and
the second stress type is tensile.
18. The electronic device of claim 14 , wherein the second layer has a pattern that is a reverse image of the first layer.
19. The electronic device of claim 14 , further comprising a second portion of the first layer, wherein:
the first and second portions of the first layer are separate and spaced apart from one another;
substantially all of the first active region is covered by the first portion of the first layer, and substantially none of the second portion of the first layer and the second layer overlies the first active region;
substantially all of the second active region is covered by the second portion of the first layer, and substantially none of the first portion of the first layer and the second layer overlies the second active region; and
substantially all of the third active region is covered by the second layer, and substantially none of the first and second portions of the first layer overlies the third active region.
20. The electronic device of claim 14 , wherein each of the first, second, and third active regions comprises a primary surface lying on a (100) or (110) crystal plane and oriented substantially in a direction of form <110>.