System and method for reducing the power consumption of clock systems
A system an method of designing an integrated circuit identifies a plurality of synchronous cells of an integrated circuit to be driven by a clock driver, wherein the plurality of synchronous cells are a subset of previously placed cells of the integrated circuit. The placement of synchronous cells is performed to reduce a current needed from the clock driver to drive the plurality of synchronous cells.
1. A method of designing an electronic device comprising:
identifying an output of a component to be coupled to a first plurality of synchronous cells;
modifying placement of the first plurality of synchronous cells at one or more locations proximate to the output, wherein modifying placement of the first plurality of synchronous cells includes placing a second plurality of synchronous cells at locations proximate to the output that results in a design rule violation for each synchronous cell of the second plurality of synchronous cells;
legalizing the second plurality of synchronous cells with respect to the design rule, wherein the second plurality of synchronous cells is a subset of the first plurality of synchronous cells and continues to be coupled to the output of the component after legalizing; and
determining if a timing constraint of the electronic device subsequent to legalizing the first plurality of synchronous cells is met.
2. The method of claim 1 , wherein identifying comprises identifying a drive cell comprising the output.
3. The method of claim 2 , further comprising placing the drive cell at a location based on a current location of the drive cell and a current location of a synchronous cell of the first plurality of synchronous cells.
4. The method of claim 1 , further comprising:
modifying a characteristic of a synchronous cell of the first plurality of synchronous cells when the timing constraint is not met.
5. The method of claim 4 , wherein the timing constraint comprises at least one of a setup time, a hold time, clock skew, and clock latency.
6. The method of claim 1 , further comprising integrating a synchronous cell of the first plurality of synchronous cells into unoccupied space proximate to the output.
7. The method of claim 1 , further comprising determining a location of a clock input pin on a synchronous cell of the first plurality of synchronous cells subsequent to legalizing and orienting the synchronous cell of the first plurality of synchronous cells to locate the clock input pin closer to the output.
8. The method of claim 1 , wherein placing comprises placing the first plurality of synchronous cells at a centroid of the first plurality of synchronous cells.
9. The method of claim 1 , further comprising determining subsequent to legalizing whether there is an orientation of a synchronous cell of the first plurality of synchronous cells that will locate a clock input node of the synchronous cell at a location that can reduce a length of a conductor in a clock tree.
10. The method of claim 1 , wherein placing the first plurality of synchronous cells at the one or more locations comprises the location being associated with a cell of the electronic device having a lower priority than the first plurality of synchronous cells.
11. A processor readable storage device comprising information to manipulate a data processor, wherein the information comprises:
control information to identify an output of a component to be coupled to a first plurality of synchronous cells;
control information to modify placement of the first plurality of synchronous cells at one or more locations proximate to the output, wherein control information to modify placement of the first plurality of synchronous cells includes control information to place a second plurality of synchronous cells at locations proximate to the output that results in a design rule violation for each synchronous cell of the second plurality of synchronous cells;
control information to legalize the second plurality of synchronous cells with respect to the design rule, wherein the second plurality of synchronous cells is a subset of the first plurality of synchronous cells and continues to be coupled to the output of the component after legalizing; and
control information to determine if a timing constraint of the electronic device subsequent to legalizing the first plurality of synchronous cells is met.
12. The processor readable storage device of claim 11 , further comprising:
control information to modify a characteristic of a synchronous cell of the first plurality of synchronous cells when the timing constraint is not met.
13. The processor readable storage device of claim 11 , further comprising control information to determine subsequent to the control information legalizing the second plurality of synchronous cells whether there is an orientation of a synchronous cell of the first plurality of synchronous cells that will locate a clock input node of the synchronous cell at a location that can reduce a length of a conductor in a clock tree.