Error detection schemes for a unified cache in a data processing system
View Patent ↗In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plurality of ways, each with one or more information fields. Cache memory control circuitry has a control register for controlling allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information. The cache memory control circuitry further individually controls a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register.
1. A data processing system comprising:
processing circuitry for executing a plurality of data processing instructions;
a unified cache memory coupled to the processing circuitry for storing data and instructions processed by the processing circuitry, the unified cache memory comprising a plurality of sets, each set comprising a plurality of ways, each way comprising one or more information fields; and
cache memory control circuitry coupled to the unified cache memory and comprising a control register for allocation control to control allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information, the cache memory control circuitry further individually controlling a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register.
2. The data processing system of claim 1 wherein the first type of information is data information and the second type of information is instruction information.
3. The data processing system of claim 2 wherein the first type of information is correlated to selecting single bit error detection and the second type of information is correlated to selecting multiple bit error detection.
4. The data processing system of claim 3 wherein the second type of information further comprises read-only data information.
5. The data processing system of claim 3 wherein the data information is modifiable data information.
6. The data processing system of claim 3 wherein the second type of information is correlated to selecting multiple bit error detection and correction.
7. The data processing system of claim 3 wherein the control register is user accessible for individually dynamically modifying the type of error detection for each of a plurality of separate ways of the unified cache memory.
8. The data processing system of claim 1 wherein the plurality of types of error detection comprise parity checking, error detection code (EDC) and error correction code (ECC).
9. A method comprising:
providing processing circuitry for executing a plurality of data processing instructions;
coupling a unified cache memory to the processing circuitry for storing data and instructions processed by the processing circuitry, the unified cache memory comprising a plurality of sets, each set comprising a plurality of ways, each way comprising one or more information fields;
coupling a cache memory control circuitry to the unified cache memory; and
providing control circuitry for allocating each way of the unified cache memory for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information, the control circuitry further individually controlling a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon a result of the allocating.
10. The method of claim 9 further comprising:
selecting the first type of information as data information; and
selecting the second type of information as instruction information.
11. The method of claim 10 further comprising:
correlating the first type of information to selecting single bit error detection as the type of error detection; and
correlating the second type of information to selecting multiple bit error detection as the type of error detection.
12. The method of claim 11 further comprising:
forming the second type of information as read-only data information.
13. The method of claim 11 further comprising:
forming the data information as modifiable data information.
14. The method of claim 11 further comprising:
correlating the second type of information to selecting multiple bit error detection and correction as the type of error detection.
15. The method of claim 11 further comprising:
individually dynamically modifying the type of error detection for each way of the unified cache memory through user access to the control circuitry.
16. The method of claim 11 further comprising:
individually selecting one of parity checking, error detection code (EDC) and error correction code (ECC) for each separate way of the unified cache memory based upon the result of the allocating.
17. A data processing system comprising:
a processing unit for executing a plurality of data processing instructions;
a unified cache memory coupled to the processing unit for storing data and instructions processed by the processing circuitry, the unified cache memory comprising a plurality of ways, each way comprising a plurality of lines, each line comprising an information field;
first control circuitry coupled to the unified cache memory and comprising an allocation control register for allocating each way of the plurality of ways for either a first type of information or a second type of information, or for both the first type of information and the second type of information; and
second control circuitry coupled to the first control circuitry for further individually selecting a mode of error detection for each way of the unified cache memory based upon the allocating performed by the first control circuitry.
18. The data processing system of claim 17 wherein the first type of information is data information that is correlated to the second control circuitry selecting single bit error detection as the mode of error detection, and the second type of information is instruction information that is correlated to the second control circuitry selecting multiple bit error detection as the mode of error detection.
19. The data processing system of claim 17 wherein the first control circuitry is user accessible for individually dynamically modifying the type of error detection for each of the plurality of ways of the unified cache memory.
20. The data processing system of claim 17 wherein the first control circuitry further comprises a storage device comprising a plurality of control fields, each of the plurality of control fields being correlated to a predetermined way of the plurality of ways of the unified cache memory for storing an encoded binary value that controls information type allocation for the predetermined way.