Error detection schemes for a cache in a data processing system
View Patent ↗A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.
1. A method, comprising:
providing a cache;
providing a plurality of cache lines within the cache,
wherein a first one of the plurality of cache lines has a tag entry and a data entry,
wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry,
wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors,
wherein both the parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines, and
wherein the first portion of the tag entry and the second portion of the tag entry are mutually exclusive portions of the tag entry;
providing a read access to the cache; and
in response to the read access resulting in a hit of the first one of the plurality of cache lines, providing the first portion of the tag entry and the one or more parity bits to parity logic which detects occurrence of a single-bit parity error in the first portion of the tag entry and providing the second portion of the tag entry and the EDC field to EDC logic which detects occurrence of a multiple-bit error in the second tag portion.
2. The method as in claim 1 , wherein the second portion of the tag entry comprises one or more tag address bits, and wherein the tag address bits are associated with the EDC field.
3. The method as in claim 1 , wherein the second portion of the tag entry comprises a valid bit, and wherein the valid bit is associated with the EDC field.
4. The method as in claim 1 , wherein the first portion of the tag entry comprises a lock bit, and wherein the lock bit is associated with the parity field.
5. The method as in claim 1 , wherein the first portion of the tag entry comprises a dirty bit, and wherein the dirty bit is associated with the parity field.
6. The method as in claim 1 , wherein the first portion of the tag entry comprises a lock bit and a dirty bit, wherein both the lock bit and the dirty bit are associated with the parity field, and wherein the parity field comprises a plurality of lock parity bits and a plurality of dirty parity bits.
7. The method as in claim 1 , wherein the cache comprises a level one cache.
8. The method as in claim 1 , wherein the cache comprises a data cache.
9. A cache, comprising:
a data array for storing a data entry, wherein the data entry is a first part of a same cache line; and
a tag array for storing a tag entry, wherein the tag entry is a second part of said same cache line,
wherein the tag entry comprises:
a parity field for storing one or more parity bits associated with a first portion of the tag entry; and
an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry,
wherein the EDC check bits are used in combination with the second portion of the tag entry for generating syndrome bits for detecting multiple bit errors,
wherein both the parity field and the EDC field are associated with said same cache line, and
wherein the first portion of the tag entry and the second portion of the tag entry are mutually exclusive.
10. The cache as in claim 9 , wherein the second portion of the tag entry comprises one or more tag address bits, and wherein the tag address bits are associated with the EDC field.
11. The cache as in claim 9 , wherein the second portion of the tag entry comprises a valid bit, and wherein the valid bit is associated with the EDC field.
12. The cache as in claim 9 , wherein the first portion of the tag entry comprises a lock bit, and wherein the lock bit is associated with the parity field.
13. The cache as in claim 9 , wherein the first portion of the tag entry comprises a dirty bit, and wherein the dirty bit is associated with the parity field.
14. The cache as in claim 9 , wherein the first portion of the tag entry comprises a lock bit and a dirty bit, wherein both the lock bit and the dirty bit are associated with the parity field, and wherein the parity field comprises a plurality of lock parity bits and a plurality of dirty parity bits.
15. The cache as in claim 9 , wherein the cache comprises a level one cache.
16. The cache as in claim 9 , wherein the cache comprises a data cache.
17. An integrated circuit comprising the cache as in claim 9 .
18. The cache as in claim 9 , further comprising:
error detection logic, coupled to the tag array, the error detection logic checking the one or more EDC check bits to detect a first error; and
parity logic, coupled to the tag array, the parity logic checking the one or more parity bits to detect a second error.
19. A method, comprising:
generating one or more lock parity bits associated with a lock bit;
generating one or more dirty parity bits associated with a dirty bit;
generating one or more EDC check bits associated with a plurality of tag address bits and a valid bit;
storing the one or more lock parity bits and the lock bit within a tag entry of a same single cache line;
storing the one or more dirty parity bits and the dirty bit within the tag entry of the same single cache line; and
storing the one or more EDC check bits, the plurality of tag address bits, and the valid bit within the tag entry of the same single cache line.
20. An integrated circuit comprising an instruction cache and a data cache,
wherein the instruction cache comprises:
a first tag array for storing first tag address information;
first parity logic, coupled to the first tag array, the first parity logic using one or more first parity bits to detect a first error in the first tag address information;
a first cache data array for storing instruction type information; and
first EDC logic, coupled to the first cache data array, the first EDC logic using a first plurality of EDC check bits to detect a second error in the instruction type information; and
wherein the data cache comprises:
a second tag array for storing second tag address information;
second EDC logic, coupled to the second tag array, the second EDC logic using a second plurality of EDC check bits to detect a third error in the second tag address information;
a second cache data array for storing data type information; and
second parity logic, coupled to the second cache data array, the second parity logic using one or more second parity bits to detect a fourth error in the data type information.