IP Library › Assignment 034749/0791
Patent Assignment
Reel/Frame 034749/0791

Assignment of Assignor's Interest

Recorded: 2015-01-07 Pages: 35
Assignor
ZENITH INVESTMENTS, LLC
Executed: 2014-12-19
Assignee
APPLE INC.
1 INFINITE LOOP, CUPERTINO, CALIFORNIA, 95014
Covered Properties (318)
Method and Apparatus for Determining Instruction Execution Ordering in a Data Processing System
Application: 07/837,470 →
Data Processing System and a Method for Cycling Longword Addresses During a Burst Bus Cycle
Patent: 5,638,528 →
Application: 08/143,731 →
Data Processing System Having a Memory with Both a High Speed Operating Mode and a Low Power Operating Mode and Method Therefor
Patent: 5,737,566 →
Application: 08/169,103 →
Write Control for a Memory Using a Delay Locked Loop
Patent: 5,440,514 →
Application: 08/207,510 →
Synchronous Memory Having Parallel Output Data Paths
Patent: 5,402,389 →
Application: 08/207,513 →
Apparatus for Detecting a Signaling Channel During Scanning Including a Controlled Frequency Converter Circuit and a Controlled Filter Bandwidth, and a Method Therefor
Patent: 5,511,235 →
Application: 08/236,736 →
System for Executing a Plurality of Task Within an Instruction in Different Orders Depending Upon a Conditional Value
Patent: 5,594,880 →
Application: 08/243,731 →
Asynchronous Transfer Mode (Atm) Method and Apparatus for Communicating Status Bytes in a Manner Compatible with the Utopia Protocol
Patent: 5,418,786 →
Application: 08/261,513 →
Method and Data Structure for Performing Address Compression in an Asynchronous Transfer Mode (Atm) System
Patent: 5,414,701 →
Application: 08/279,140 →
Method and Apparatus for Estimating Echo Cancellation Time
Patent: 5,502,717 →
Application: 08/283,322 →
Method and Apparatus for Pacing Asynchronous Transfer Mode (Atm) Data Cell Transmission
Patent: 5,491,691 →
Application: 08/291,225 →
Modular Chip Select Control Circuit and Method for Performing Pipelined Memory Accesses
Patent: 5,617,559 →
Application: 08/298,868 →
Integrated Circuit Microprocessor with Programmable Memory Access Interface Types
Patent: 5,727,005 →
Application: 08/298,892 →
Method and Structure for Prioritizing Performance Monitoring Cells in an Asynchronous Transfer Mode (Atm) System
Patent: 5,717,858 →
Application: 08/324,192 →
Asynchronous Transfer Mode (Atm) System Having an Atm Device Coupled to Multiple Physical Layer Devices
Patent: 5,485,456 →
Application: 08/326,972 →
Dsp Co-Processor for Use on an Integrated Circuit That Performs Multiple Communication Tasks
Patent: 5,652,903 →
Application: 08/332,971 →
Integrated Circuit That Performs Multiple Communication Tasks
Patent: 5,621,800 →
Application: 08/333,152 →
Method and Apparatus for Extracting Digital Information from an Asynchronous Data Stream
Patent: 5,504,751 →
Application: 08/334,975 →
Method for Synchronously Accessing Memory
Application: 08/353,764 →
Data Processor with Controlled Burst Memory Accesses and Method Therefor
Patent: 5,651,138 →
Application: 08/363,423 →
Transconductance Scaling Circuit and Method Responsive to a Received Digital Code Word for Use with an Operational Transconductance Circuit
Patent: 5,530,399 →
Application: 08/363,786 →
Method and Apparatus for Identifying Embedded Framing Bits
Patent: 5,557,615 →
Application: 08/368,284 →
Method and Apparatus for a Dmt Receiver Having a Data De-Formatter Coupled Directly to a Constellation Decoder
Patent: 5,539,777 →
Application: 08/378,431 →
Method for Producing and Recovering a Data Stream for a Dmt Transceiver
Patent: 5,619,505 →
Application: 08/378,697 →
Method and Apparatus for Updating Carrier Channel Allocations
Patent: 5,521,906 →
Application: 08/378,846 →
Method and Apparatus for a Dmt Transmitter Having a Data Formatter Coupled Directly to a Constellation Encoder
Patent: 5,606,577 →
Application: 08/378,847 →
Method and Apparatus for Reducing Peak-to-Average Requirements in Multi-Tone Communication Circuits
Patent: 5,835,536 →
Application: 08/383,026 →
Method and Apparatus for Distributing Bus Loading in a Data Processing System
Patent: 5,638,520 →
Application: 08/414,473 →
Method and Apparatus for Interleave/De-Interleave Addressing in Data Communication Circuits
Patent: 5,636,224 →
Application: 08/430,668 →
Data Processor with a Multi-Level Protection Mechanism, Multi-Level Protection Circuit, and Method Therefor
Patent: 5,649,159 →
Application: 08/445,817 →
Method and Apparatus for Controlling Show Cycles in a Data Processing System
Patent: 5,675,749 →
Application: 08/460,484 →
Reset Configuration in a Data Processing System and Method Therefor
Patent: 5,623,687 →
Application: 08/494,664 →
Data Processing System and a Method of Optimizing an Operation of the Data Processing System
Patent: 5,812,871 →
Application: 08/497,571 →
Method and Apparatus for Providing Low Power Control of Peripheral Devices Using the Register File of a Microprocessor
Patent: 5,689,714 →
Application: 08/520,121 →
A Data Processing System for Accessing an External Device During a Burst Mode of Operation and Method Therefor
Patent: 5,752,267 →
Application: 08/534,763 →
Method and Apparatus for Bursting Operand Transfers During Dynamic Bus Sizing
Patent: 5,689,659 →
Application: 08/550,043 →
Synchronization of Transparent Tdm Superchannels
Patent: 5,668,807 →
Application: 08/566,418 →
Multichannel Hdlc Framing/Deframing Machine
Patent: 5,671,223 →
Application: 08/566,444 →
Circuit and Method of Encoding and Decoding Digital Data Transmitted Along Optical Fibers
Patent: 5,673,130 →
Application: 08/582,841 →
Data Processing System Having a Register Controllable Speed
Patent: 5,774,703 →
Application: 08/583,259 →
Data Processing System Having Programmable External Terminals Such That the External Terminals Are Selectively Subjected to Bus Arbitration
Patent: 5,737,584 →
Application: 08/589,699 →
Data Processor with Flexible Data Encryption
Patent: 5,892,826 →
Application: 08/593,987 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent: 5,787,291 →
Application: 08/598,833 →
Memory System Ensuring Coherency for Memory Buffers in a Data Communication System
Patent: 5,721,871 →
Application: 08/598,934 →
Memory System and Data Communications System
Patent: 5,710,944 →
Application: 08/599,016 →
Method and Apparatus for Reducing Power Consumption in a Communications System
Patent: 5,722,086 →
Application: 08/603,109 →
Flexible Asymmetrical Digital Subscriber Line (Adsl) Receiver, Central Office Using Same, and Method Therefor
Patent: 5,742,527 →
Application: 08/616,818 →
Flexible Asymmetrical Digital Subscriber Line Adsl) Transmitter, Remote Terminal Using Same, and Method Therefor
Patent: 5,781,728 →
Application: 08/616,819 →
Method and Apparatus for Performing Page Mode Accesses
Patent: 5,890,196 →
Application: 08/623,499 →
Improved Cache Memory in a Data Processing System
Patent: 5,765,190 →
Application: 08/629,927 →
Apparatus and Method for Optimizing Performance of a Cache Memory in a Data Processing System
Patent: 6,192,449 →
Application: 08/629,930 →
Flexible Reset Configuration of a Data Processing System and Method Therefor
Patent: 5,606,715 →
Application: 08/639,461 →
Transfer Rate Controller and Method of Operation
Patent: 5,889,763 →
Application: 08/658,046 →
Method for Allocating Data in a Data Communication System
Patent: 5,852,633 →
Application: 08/660,380 →
Method for Fine Gains Adjustment in an Adsl Communications System
Patent: 5,822,374 →
Application: 08/660,399 →
Digitally Implemented Frequency Multiplication Circuit Having Adjustable Multiplication Ratio and Method of Operation
Patent: 5,729,166 →
Application: 08/660,779 →
Method and Apparatus for Performing Different Cache Replacement Algorithms for Flush and Non-Flush Operations in Response to a Cache Flush Control Bit Register
Patent: 5,778,432 →
Application: 08/674,050 →
Method and Apparatus for Burst Protocol in a Data Processing System
Patent: 6,085,261 →
Application: 08/690,463 →
Method and Apparatus for Selectively Programming Access Time in a Data Processor
Patent: 6,076,170 →
Application: 08/711,517 →
Apparatus and Method for Clock Recovery in a Communication System
Patent: 5,898,744 →
Application: 08/722,433 →
Method and Apparatus for Interleaving Data in an Asymmetric Digital Subscriber Line (Adsl) Transmitter
Patent: 5,737,337 →
Application: 08/723,032 →
Interface for an Asymmetric Digital Subscriber Line Transceiver
Patent: 5,825,768 →
Application: 08/723,437 →
Method and Apparatus for Frequency Domain Ripple Compensation for a Communications Transmitter
Patent: 5,825,826 →
Application: 08/724,097 →
Method and Apparatus for Controlling Bus Arbitration in a Data Processing System
Patent: 5,894,562 →
Application: 08/738,515 →
Method and Apparatus for Performing Frame Synchronization in an Asymmetrical Digital Subscriber Line (Adsl) System
Patent: 5,995,568 →
Application: 08/740,176 →
Single-Chip Software Configurable Transceiver for Asymmetric Communication System
Patent: 5,909,463 →
Application: 08/741,634 →
Apparatus and Method for Auto-Configuring a Communication System
Patent: 5,960,036 →
Application: 08/741,635 →
Transceiver and Method for Reporting State Transitions in a Communication System
Patent: 5,903,599 →
Application: 08/744,078 →
Rate-Adapted Communication System and Method for Efficient Buffer Utilization Thereof
Patent: 5,751,741 →
Application: 08/754,768 →
Transfer Layer of the Atm Type and Method for Operating a Transfer Switch
Patent: 5,892,755 →
Application: 08/768,013 →
Method and Apparatus for Interleave/De-Interleave Addressing in Data Communication Circuits
Patent: 5,886,998 →
Application: 08/797,439 →
Dual Modulus Prescaler
Patent: 5,859,890 →
Application: 08/806,811 →
System Power Saving Means and Method
Patent: 5,887,179 →
Application: 08/807,129 →
Asymmetrical Digital Subscriber Line (Adsl) Block Encoder Circuit and Method of Operation
Patent: 5,883,907 →
Application: 08/848,902 →
Modular Switch Element for Shared Memory Switch Fabric
Patent: 5,859,849 →
Application: 08/851,731 →
Atm Line Card and Method for Transferring Connection Memory Data
Patent: 5,923,658 →
Application: 08/856,835 →
Method for Accessing Memory Using Overlapping Accesses and Early Synchronous Data Transfer Control
Patent: 6,079,001 →
Application: 08/868,622 →
Method and Apparatus for Controlling a Memory Device in a Page Mode
Patent: 5,848,025 →
Application: 08/885,434 →
Method and Apparatus for Providing Access Protection in an Integrated Circuit
Patent: 5,920,690 →
Application: 08/907,980 →
Systems for Programmably Interleaving and De-Interleaving Data and Method Thereof
Patent: 5,928,371 →
Application: 08/910,475 →
Method for Digital Signal Processing, Dsp, Mobile Communication and Audio-Device
Patent: 6,145,070 →
Application: 08/912,243 →
Method and Appartus for Suspending a Program/Erase Operation in a Flash Memory
Patent: 5,822,244 →
Application: 08/936,373 →
Method and Apparatus for Configuring a Communication System
Patent: 6,130,882 →
Application: 08/937,759 →
Method for Reallocating Data in a Discrete Multi-Tone Communication System
Patent: 6,122,247 →
Application: 08/976,472 →
Transmitter and Receiver Supporting Differing Speed Codecs Over Single Links
Patent: 6,128,317 →
Application: 08/996,165 →
Method for Allocating Data and Power in a Discrete Multi-Tone Communcation System
Patent: 6,259,746 →
Application: 09/007,218 →
Method for Allocating Data and Power in a Discrete, Multi-Tone Communication System
Patent: 6,275,522 →
Application: 09/007,390 →
Paged Memory Data Processing System with Overlaid Memory Control Registers
Patent: 6,058,463 →
Application: 09/009,509 →
Memory Controller with Continuous Page Mode and Method Thereof
Patent: 6,128,716 →
Application: 09/010,976 →
Apparatus and Method for Transmitting Data
Patent: 6,167,059 →
Application: 09/013,048 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent: 5,951,688 →
Application: 09/024,607 →
Method and Apparatus in a Communication Receiver for Estimating Symbol Timing and Carrier Frequency
Patent: 6,091,786 →
Application: 09/048,040 →
System and Method of Communicating Non-Standardized Addresses Over a Standardized Carrier Network
Patent: 6,556,584 →
Application: 09/055,455 →
Control Circuit and Method for a Temperature Sensitive Device
Patent: 5,973,528 →
Application: 09/061,299 →
Sigma-Delta Modulator and Method for Digitizing a Signal
Patent: 6,087,969 →
Application: 09/067,147 →
Customizable Instruction Set Processor with Non-Configurable/Configurable Decoding Units and Non-Configurable/Configuravble Execution Units
Patent: 6,138,229 →
Application: 09/086,741 →
Data Processing System Having a Data Prefetch Mechanism and Method Therefor
Patent: 6,073,215 →
Application: 09/127,884 →
Method for Monitoring Unused Bins in a Discrete Multi-Toned Communication System
Patent: 6,452,907 →
Application: 09/173,380 →
Line Driver Circuit with Reduced Power Consumption
Patent: 6,100,717 →
Application: 09/174,148 →
Dual Channel Superheterodyne Receiver
Patent: 6,259,902 →
Application: 09/181,760 →
Method and System for Modifying Executable Code to Add Additional Functionality
Application: 09/212,182 →
Publication: US 2002/0073398
Communication System with Physical Interface and Communication Controller, and Method
Patent: 6,574,228 →
Application: 09/241,195 →
Electronic Apparatus and Method for Receiving Noisy Signals
Patent: 6,529,567 →
Application: 09/265,221 →
Circuit and Method of Controlling Cache Memory
Patent: 6,279,083 →
Application: 09/275,617 →
High Performance Communication Controller for Processing High Speed Data Streams Wherein Execution of a Task Can Be Skipped If Involves Fetching Information from External Memory Bank
Patent: 6,473,808 →
Application: 09/285,519 →
Method for Determining the Number of Accesses Granted During Wcl and Apparatus
Patent: 6,580,719 →
Application: 09/297,854 →
Fast Training of Equalizers in Discrete Multi-Tone (Dmt) Systems
Patent: 6,535,552 →
Application: 09/314,587 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent: 6,119,240 →
Application: 09/321,389 →
Communication System with Communication Controller and Multiple Physical Interfaces, and Method
Patent: 6,490,283 →
Application: 09/348,101 →
Adjustable Power Control Module and Applications Thereof
Patent: 6,137,279 →
Application: 09/376,501 →
Method and Apparatus for Data Allocation in an Overlap-Enabled Communication System
Application: 09/379,081 →
Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
Patent: 6,892,339 →
Application: 09/398,707 →
Method and Apparatus for Echo Cancellation Updates in a Multicarrier Transceiver System
Patent: 6,683,859 →
Application: 09/438,619 →
Bus Arbitration in Low Power System
Patent: 6,560,712 →
Application: 09/440,857 →
Low Overhead Method for Selecting and Updating an Entry in a Cache Memory
Patent: 6,519,684 →
Application: 09/447,254 →
Method and Apparatus for Configuring a Communication System
Patent: 6,775,241 →
Application: 09/451,532 →
High frequency detection circuit and method
Patent: 6,259,279 →
Application: 09/493,585 →
Reassembly Unit and a Method Thereof
Patent: 6,665,298 →
Application: 09/494,601 →
Method for digital signal processing,dsp,mobile communication and audio-device
Patent: 6,282,623 →
Application: 09/497,986 →
Method and Apparatus for Overlaying Memory in a Data Processing System
Patent: 6,725,346 →
Application: 09/542,747 →
Method and Apparatus for Echo Cancellation Updates in a Multicarrier Transceiver System
Patent: 6,781,965 →
Application: 09/543,866 →
Method and Apparatus for Performing Hierarchical Address Translation
Patent: 6,711,661 →
Application: 09/606,995 →
Single Instruction for Multiple Loops
Patent: 6,842,895 →
Application: 09/746,978 →
Publication: US 2002/0083305
Method and Circuit for Forming an Atm Cell
Patent: 6,826,188 →
Application: 09/764,967 →
Publication: US 2002/0093962
Method and Apparatus for Analog to Digital Conversion Utilizing a Moving Sum
Patent: 6,567,027 →
Application: 09/779,810 →
Publication: US 2002/0145547
Memory Interface Protocol Using Two Addressing Modes and Method of Operation
Patent: 6,574,707 →
Application: 09/849,704 →
Publication: US 2002/0166028
System and Method for Controlling Bus Arbitration During Cache Memory Burst Cycles
Patent: 6,775,727 →
Application: 09/888,278 →
Publication: US 2002/0199052
Apparatus and Method to Synchronize Multimedia Playback Over a Network Using Out-of-Band Signaling
Patent: 7,206,367 →
Application: 09/903,040 →
Phase Excited Linear Prediction Encoder
Patent: 6,871,176 →
Application: 09/915,893 →
Publication: US 2003/0074192
Method and Apparatus for Managing Multicast Data on an Ip Subnet
Patent: 7,177,318 →
Application: 09/929,211 →
Publication: US 2003/0035378
Cpu Powerdown Method and Apparatus Therefor
Patent: 7,539,878 →
Application: 09/956,300 →
Publication: US 2003/0056127
Autogenerated Play Lists from Search Criteria
Patent: 7,143,102 →
Application: 09/967,793 →
Publication: US 2003/0065639
Memory Having a Synchronous Controller and Asynchronous Array and Method Thereof
Patent: 6,490,225 →
Application: 10/004,721 →
Simple Encoding/Decoding Technique for Code Position Modulation
Patent: 6,594,317 →
Application: 10/029,038 →
Publication: US 2003/0035489
Method and System for Accessing Memory Devices
Patent: 7,080,191 →
Application: 10/034,834 →
Publication: US 2003/0126350
Method and Apparatus for Generating a Pulse Width Modulated Signal
Patent: 6,606,044 →
Application: 10/034,909 →
Publication: US 2003/0122692
Interfacing a Processor to a Coprocessor in Which the Processor Selectively Broadcasts to or Selectively Alters an Execution Mode of the Coprocessor
Patent: 7,228,401 →
Application: 10/054,577 →
Publication: US 2003/0093648
Low Power System and Method for a Data Processing System
Patent: 7,155,618 →
Application: 10/094,053 →
Publication: US 2003/0172310
Data Processing System with Peripheral Access Protection and Method Therefor
Patent: 7,277,972 →
Application: 10/094,082 →
Publication: US 2003/0172214
System and Apparatus for Reducing the Effects of Circuit Mismatch in Analog-to-Digital Converters
Patent: 7,075,473 →
Application: 10/135,789 →
Publication: US 2003/0201928
Data Transfer Unit with Support for Multiple Coherency Granules
Patent: 6,847,990 →
Application: 10/150,671 →
Publication: US 2003/0217232
Method and Apparatus for Determining Whether a Received Signal Includes a Desired Signal
Patent: 7,035,319 →
Application: 10/210,348 →
Publication: US 2004/0022301
Passive Response Communication System
Patent: 6,992,568 →
Application: 10/228,518 →
Publication: US 2003/0043023
Performance Monitor and Method Therefor
Patent: 6,937,961 →
Application: 10/255,427 →
Publication: US 2004/0064290
Shared Write Buffer in a Peripheral Interface and Method of Operating
Patent: 7,096,307 →
Application: 10/323,313 →
Publication: US 2004/0123010
Continuous-Time Sigma-Delta Modulator with Discrete Time Common-Mode Feedback
Patent: 6,697,001 →
Application: 10/324,684 →
Method and System for Modifying Executable Code to Add Additional Functionality
Patent: 6,948,164 →
Application: 10/369,225 →
Publication: US 2003/0212983
Bus Arbitration in Low Power System
Patent: 7,188,262 →
Application: 10/376,816 →
Publication: US 2003/0140263
Method and System of Bus Master Arbitration
Patent: 7,099,973 →
Application: 10/402,165 →
Publication: US 2004/0193766
Low-Complexity Comfort Noise Generator
Patent: 7,243,065 →
Application: 10/408,996 →
Publication: US 2004/0204934
Manipulating data streams in data stream processors
Application: 10/475,066 →
Publication: US 2004/0260829
Passive Communication Device and Passive Access Control System
Patent: 7,286,042 →
Application: 10/481,111 →
Publication: US 2005/0052286
Controlling Power Supply Between a Voltage Generator, a Load and a Rechargeable Battery
Patent: 7,706,758 →
Application: 10/497,426 →
Publication: US 2005/0105656
I/Q Mismatch Compensation in an Ofdm Receiver in Presence of Frequency Offset
Patent: 7,443,783 →
Application: 10/504,456 →
Publication: US 2005/0152463
Channel Estimation in a Radio Receiver
Patent: 7,965,796 →
Application: 10/505,999 →
Publication: US 2005/0232377
Transmitter and Receiver Gain Calibration by Means of Feedback in a Transceiver
Patent: 7,567,788 →
Application: 10/521,417 →
Publication: US 2007/0129031
Arrangement and Method for Connecting a Processing Node in a Distribution System
Patent: 7,818,613 →
Application: 10/567,309 →
Publication: US 2006/0274790
A Multimode Decoder
Patent: 7,652,597 →
Application: 10/596,367 →
Publication: US 2009/0015448
Multi-Standard Turbo Interleaver Using Tables
Patent: 7,734,989 →
Application: 10/596,369 →
Publication: US 2007/0101231
Method and Apparatus for Accurate Digital-to-Analog Conversion
Patent: 6,778,119 →
Application: 10/603,544 →
Publication: US 2004/0104830
Variable Bandgap Reference and Applications Thereof
Patent: 6,859,156 →
Application: 10/603,545 →
Publication: US 2004/0104831
Method and Apparatus for Current Limiting of an Output of a Dc-to-Dc Converter
Patent: 7,046,530 →
Application: 10/603,547 →
Publication: US 2004/0105284
Low Loss Multiple Output Stage for a Dc-to-Dc Converter
Patent: 6,853,171 →
Application: 10/603,555 →
Publication: US 2004/0114406
Method and apparatus for efficient battery use by a handheld multiple function device
Application: 10/603,640 →
Publication: US 2004/0104707
Conserving Power of a System on a Chip Using an Alternate Power Source
Patent: 7,259,480 →
Application: 10/607,948 →
Publication: US 2004/0113497
Conserving Power of a System on a Chip Using Speed Sensing
Patent: 7,036,029 →
Application: 10/607,960 →
Publication: US 2004/0268165
Programmable Phase Mapping and Phase Rotation Modulator and Method
Patent: 7,412,008 →
Application: 10/610,116 →
Publication: US 2004/0264599
Battery-Optimized System-on-a-Chip and Applications Thereof
Patent: 7,278,119 →
Application: 10/612,577 →
Publication: US 2004/0107407
Multi-Mode Method and Apparatus for Performing Digital Modulation and Demodulation
Patent: 7,406,102 →
Application: 10/613,476 →
Publication: US 2004/0071104
Searching Method and Apparatus for Processing Digital Communication Signals
Patent: 7,702,035 →
Application: 10/613,477 →
Publication: US 2004/0004997
Virtual finger method and apparatus for processing digital communication signals
Application: 10/613,825 →
Publication: US 2004/0071199
Flexible Method and Apparatus for Performing Digital Modulation and Demodulation
Patent: 7,596,134 →
Application: 10/613,853 →
Publication: US 2004/0047405
Buffering Method and Apparatus for Processing Digital Communication Signals
Patent: 7,912,999 →
Application: 10/613,897 →
Publication: US 2004/0004995
Conditional Next Portion Transferring of Data Stream to or from Register Based on Subsequent Instruction Aspect.
Patent: 7,107,436 →
Application: 10/657,593 →
Publication: US 2005/0055534
Method and Circuitry for Controlling Supply Voltage in a Data Processing System
Patent: 7,085,943 →
Application: 10/672,161 →
Publication: US 2005/0071693
Communication steering for use in a multi-master shared resource system
Application: 10/682,571 →
Publication: US 2005/0080961
Data Processing System Having a Serial Data Controller
Patent: 7,047,350 →
Application: 10/683,778 →
Publication: US 2005/0080975
On-Chip Digital Thermometer to Sense and Measure Device Temperatures
Patent: 7,104,684 →
Application: 10/718,769 →
Publication: US 2004/0105488
On-Chip Realtime Clock Module Has Input Buffer Receiving Operational and Timing Parameters and Output Buffer Retrieving the Parameters
Patent: 7,234,071 →
Application: 10/720,785 →
Publication: US 2004/0107373
System and Method to Establish an Adjustable on-Chip Impedance
Patent: 6,940,303 →
Application: 10/721,203 →
Publication: US 2004/0104757
Microphone Bias Circuit
Patent: 7,372,967 →
Application: 10/723,170 →
Publication: US 2004/0208327
Amplifier Having Mos Capacitor Compensation
Patent: 6,906,591 →
Application: 10/723,492 →
Publication: US 2004/0108899
Configurable Integrated Circuit for Use in a Multi-Function Handheld Device
Patent: 6,998,871 →
Application: 10/723,634 →
Publication: US 2004/0107303
Method for Initializing Multifunction Handheld Device by Downloading Second Boot Algorithm from a Coupled Host If Second Boot Algorithm in the Handheld Device Is Not Executable
Patent: 7,210,032 →
Application: 10/723,665 →
Publication: US 2004/0111598
System and Method to Initialize a Multiple Function Device with a Multi-Part Boot Algorithm
Patent: 7,430,659 →
Application: 10/723,706 →
Publication: US 2004/0111599
Use of a Resource Identifier to Import a Program from External Memory for an Overlay
Patent: 7,130,980 →
Application: 10/723,710 →
Publication: US 2004/0111574
Use of Multiple Overlays to Import Programs from External Memory
Patent: 7,424,588 →
Application: 10/723,781 →
Publication: US 2004/0107328
Use of Nand Flash for Hidden Memory Blocks to Store an Operating System Program
Patent: 7,203,828 →
Application: 10/723,909 →
Publication: US 2004/0133734
Esd Protection Circuit
Patent: 7,164,565 →
Application: 10/723,965 →
Publication: US 2004/0109271
Method and Apparatus for Processing a Frequency Modulated (Fm) Signal Using an Adaptive Equalizer
Patent: 7,697,898 →
Application: 10/779,217 →
Publication: US 2005/0181741
Method and Apparatus for Complex Cascade Sigma-Delta Modulation and Single-Sideband Analog-to-Digital Conversion
Patent: 7,180,432 →
Application: 10/788,588 →
Publication: US 2005/0191980
State Retention Within a Data Processing System
Patent: 7,365,596 →
Application: 10/819,383 →
Publication: US 2005/0218943
Prefetching in a Data Processing System
Patent: 7,249,223 →
Application: 10/916,298 →
Publication: US 2006/0036812
Variable Bandgap Reference
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Data Processing System with Bus Access Retraction
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Data Processing System with Bus Access Retraction
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Method and Apparatus for Data Allocation in an Overlap-Enabled Communication System
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Receiver for a Wireless Communication Device
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High Resolution Pulse Width Modulator
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Fully Programmable Phase Locked Loop
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Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
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Methods and Apparatus for Bit Synchronizing Data Transferred Across a Multi-Pin Asynchronous Serial Interface
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Dc Offset Correction System for a Receiver with Baseband Gain Control
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System and Method for Accessing Universal Serial Bus Networks
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Controllable Phase Locked Loop with Output Oscillation Adjustment and Method for Producing an Output Oscillation for Use Therewith
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Method and Apparatus for Digitally Regulating an Output Voltage Using Noise-Shaped Component Selection
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Temperature Sensor Circuit and System
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Extending Battery Life in Communication Devices Having a Plurality of Receivers
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Programmable Sample Rate Analog to Digital Converter and Method for Use Therewith
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Controllable Phase Locked Loop via Adjustable Delay and Method for Producing an Output Oscillation for Use Therewith
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System and Method for Scheduling Access to an Analog-to-Digital Converter and a Microprocessor
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A Configurable Integrated Circuit for Use in a Multi-Function Handheld Device
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One Time Programmable Memory and Method of Operation
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System and Method for Wireless Broadband Context Switching
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Convolution Operation in a Multi-Mode Wireless Processing System
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Modulation Detection in a Saic Operational Environment
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Priority Queuing of Frames in a Tdma Network
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Dynamic Switching Between Maximum Likelihood Sequence Estimation (Mlse) and Linear Equalizer for Single Antenna Interference Cancellation (Saic) in a Global System for Mobile Communications (Gsm) System
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Method & Apparatus for Power Supply Adjustment with Increased Slewing
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Controlled Sampling Module and Method for Use Therewith
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Media-Independent Handover (Mih) Method Featuring a Simplified Beacon
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Multiple Function Handheld Device
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Selective Transaction Request Processing at an Interconnect During a Lockout
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Clock Translator and Parallel to Serial Converter
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Selective Cache Line Allocation Instruction Execution and Circuitry
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Comparative Signal Strength Detection
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System and Method for Operating a Feedback Network
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Headphone Driver and Methods for Use Therewith
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Mitigation of Dc Distortion in Ofdm Receivers
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Digital Audio System on a Chip
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Method and Integrated Circuit for Use by a Handheld Multiple Function Device
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Audio System, Radio Record Module and Methods for Use Therewith
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Audio System, Radio Record Module and Methods for Use Therewith
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System and Method for Scheduling Access to an Analog-to-Digital Converter and a Microprocessor
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System and Method for Implementing Acls Using Standard Lpm Engine
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Lookup Table Array Compression and Indexing
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Coprocessor Receiving Target Address to Process a Function and to Send Data Transfer Instructions to Main Processor for Execution to Preserve Cache Coherence
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Circuit for use in a multifunction handheld device with wireless host interface
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Circuit for use in multifunction handheld device having a radio receiver
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Circuit for use in cellular telephone with video functionality
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Circuit for Use with Multifunction Handheld Device with Video Functionality
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Re-Configurable Impedance Matching and Harmonic Filter System
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Controlled Sampling Module and Method for Use Therewith
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Continuous Time Noise Shaping Analog-to-Digital Converter
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Data Stream Processing Method and System
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Digital Audio System on a Chip with Configurable Gpios
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Integrated Circuit Temperature Sensing Method
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Resource Allocation in Multi Data Stream Communication Link
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System and Method for Scheduling Access to an Analog-to-Digital Converter and a Microprocessor
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Controlling the Bandwidth of an Analog Filter
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System and Method for Reporting Cache Coherency State Retained Within a Cache Hierarchy of a Processing Node
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Wireless Communication Unit and Method for Processing a Code Division Multiple Access Signal
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Wireless Communication Device and Data Interface
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Apparatus and Method for Controlling Voltage and Frequency
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Methods and Apparatus for Round Trip Time Measurements
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Methods and Apparatus for a Spread Spectrum Switching Regulator
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Parallel Processing for Single Antenna Interference Cancellation
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Digital Audio Processing System and Method
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Automatically Disabling Input/Output Signal Processing Based on the Required Multimedia Format
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Joint De-Spreading and Frequency Correction Using a Correlator
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Interprocessor Message Transmission via Coherency-Based Interconnect
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Reference Signal Selection Techniques for a Wireless Communication System
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System and Method for Receiving a Multiple Format Wireless Signal
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System and Method for Monitoring Network Traffic
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Wireless Communication Unit and Power Control System Thereof
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Adaptive Equalizer for Communication Channels
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Wireless Transceiver and Method for Use Therewith
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Wireless Handset and Wireless Headset with Wireless Transceiver
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Method and circuit for use by a handheld multiple function device
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Use of Nand Flash for Hidden Memory Blocks to Store an Operating System Program
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Controllable Oscillator with Output Oscillation Adjustment and Method for Producing an Output Oscillation for Use Therewith
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Programmable Sample Rate Analog to Digital Converter and Method for Use Therewith
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Discrete Dithered Frequency Pulse Width Modulation
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Method of Transitioning Between Active Mode and Power-Down Mode in Processor Based System
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Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
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Battery Optimized Circuit and System on a Chip
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System on a Chip with Multiple Independent Outputs
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Cache Locking Device and Methods Thereof
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Digital Audio Amplifiers, Electronic Systems, and Methods
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System-On-A-Chip for Processing Multimedia Data and Applications Thereof
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System and Method for Handling or Avoiding Disruptions in Wireless Communication
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Gain Control Methods for Wireless Devices and Transmitters
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Gmsk-Receiver with Interference Cancellation
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Diversity Gmsk-Receiver with Interference Cancellation and Methods Therein
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Adaptive Pre-Distortion with Interference Detection and Mitigation
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Initiation of High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
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High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
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Data Arbitration on a Bus to Determine an Extreme Value
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Techniques for Compressing Differential Samples of Bandwidth-Limited Data to Reduce Bandwidth and Power Consumption by an Interface
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Wireless Communication Unit, Integrated Circuit and Biasing Therefor
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Power Amplifiers Having Improved Startup Linearization and Related Operating Methods
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Groups of Serially Coupled Processor Cores Propagating Memory Write Packet While Maintaining Coherency Within Each Group Towards a Switch Coupled to Memory Partitions
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Automatically Disabling Input/Output Signal Processing Based on the Required Multimedia Format
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Hybrid Polyphase and Joint Time-Frequency Detection
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Method for Managing Under-Runs and a Device Having Under-Run Management Capabilities
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Method for High Speed Framing and a Device Having Framing Capabilities
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Techniques for Calibrating a Transceiver of a Communication Device
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Gain Control Methods for Wireless Devices and Transmitters
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Systems and Methods of Parallel to Serial Conversion
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Systems and Methods for Adjusting Headroom of a Power Amplifier
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Communication Steering for Use in a Multi-Master Shared Resource System
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Method for Exchanging Information with Physical Layer Component Registers
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Power Amplifier with Pre-Distorter
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Method for Transmitting Data from Multiple Clock Domains and a Device Having Data Transmission Capabilities
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Method for Processing Information Fragments and a Device Having Information Fragment Processing Capabilities
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Spread Spectrum Pulse Width Modulation Method and Apparatus
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Manipulating Data Streams in Data Stream Processors
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Comparative Signal Strength Detection
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Digital Audio Processing System and Method
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Coherency Groups of Serially Coupled Processing Cores Propagating Coherency Information Containing Write Packet to Memory
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Digital Audio Processing System and Method
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Related Assignments (9)
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Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
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Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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Assignment and Assumption of Security Interest in Patents Jan 12, 2016
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Release of Security Interest Sep 21, 2016
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Release of Security Interest Nov 7, 2016
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