Parallel processing for single antenna interference cancellation
View Patent ↗A system and method is disclosed for providing single antenna interference cancellation processing with minimum latency. Incoming data frames are processed to generate a plurality of parallel data streams which are then further processed using a parallel single antenna interference cancellation algorithm to reject the signals and to generate a data stream containing only the desired symbols. In various embodiments of the invention, the parallel data streams are processed using a parallel arithmetic logic unit that is capable of operating in single-cycle mode in response to a first control stream and a multi-cycle mode in response to a second control stream. Embodiments of the invention comprise a three port memory interface operable to receive the parallel data streams and to generate a virtual three-dimensional data structure therefrom. In some embodiments of the invention, the virtual three-dimensional data representation comprises a plurality of segmented matrices, with the segmented matrices comprising data corresponding to portions of the incoming data frames. Data elements within the individual segments of the virtual three dimensional data structure can be calculated using data elements contained in a predetermined row and predetermined column of a segment.
1. A method of canceling interference in a data communication system, comprising:
receiving a plurality of incoming data frames, said data frames comprising desired data and undesired interference;
using a processor to process said data frames to generate a plurality of parallel data streams; and
using said processor to process said parallel data streams using a parallel single-antenna interference cancellation algorithm, to reject said undesired interference and to generate a data stream containing said desired data;
using said processor to process said parallel data streams to generate a virtual three-dimensional data representation of data comprising said incoming data frames;
wherein said virtual three-dimensional data representation comprises a plurality of segmented matrices, said segmented matrices comprising data corresponding to segments of said incoming data frames; and
wherein each of said segmented matrices comprise physically stored data for data elements defining one predetermined row and one predetermined column thereof.
2. The method of claim 1 , wherein said parallel data streams are processed using a parallel arithmetic logic unit.
3. The method of claim 1 , wherein said parallel arithmetic logic unit is operable to perform single-cycle arithmetic operations in response to a first control stream and to perform multi-cycle arithmetic operations in response to a second control stream.
4. The method of claim 1 , wherein said parallel data streams are processed using a three port memory interface.
5. The method of claim 4 , wherein the three port memory interface comprises single-port shared system memory and dual-port memory.
6. The method of claim 1 , wherein at least one dimension of said virtual three-dimensional data representation corresponds to delay parameters associated with said incoming data frames.
7. The method of claim 1 , wherein said plurality of segments comprises derotated training sequence (TSC) data.
8. The method of claim 1 , wherein a desired data element not located on said predetermined row or predetermined column is calculated using a relative offset of said desired data element with respect to a data element located on said predetermined row or predetermined column.
9. A system for canceling interference in data communications, comprising:
a receiver module operable to receive a plurality of incoming data frames, said data frames comprising desired data and undesired interference;
a processor operable to process said incoming data frames to generate a plurality of parallel data streams, to store data elements comprising said parallel data streams, to implement a parallel single-antenna interference cancellation algorithm to eliminate said undesired interference, and to generate a data stream containing said desired data; and to process said parallel data streams to generate a virtual three-dimensional data representation of data comprising said incoming data frames;
wherein said virtual three-dimensional data representation comprises a plurality of segmented matrices, said segmented matrices comprising data corresponding to segments of said incoming data frames; and
wherein each of said segmented matrices comprise physically stored data for data elements defining one predetermined row and one predetermined column thereof.
10. The system according to claim 9 , wherein said parallel data streams are processed using a parallel arithmetic logic unit.
11. The system according to claim 10 , wherein said parallel arithmetic logic unit is operable to perform single-cycle arithmetic operations in response to a first control stream and to perform multi-cycle arithmetic operations in response to a second control stream.
12. The system of claim 9 , wherein said memory logic comprises a three port memory interface.
13. The system of claim 12 , wherein said three port memory interface comprises single-port shared system memory and dual-port memory.
14. The system of claim 13 , wherein at least one dimension of said virtual three-dimensional data representation corresponds to delay parameters associated with said incoming data frames.
15. The system of claim 13 , wherein said plurality of segments comprises derotated training sequence (TSC) data.
16. The system of claim 9 , wherein a desired data element not located on said predetermined row or predetermined column is calculated using a relative offset of said desired data element with respect to a data element located on said predetermined row or predetermined column.