Patent Assignment
Reel/Frame 033687/0336
Assignment of Assignor's Interest
Recorded: 2014-09-04
Pages: 41
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2013-11-28
Assignee
ZENITH INVESTMENTS, LLC
1209 ORANGE STREET, WILMINGTON, DELAWARE, 19801
Covered Properties
(131)
Data Processing System and a Method for Cycling Longword Addresses During a Burst Bus Cycle
Patent:
5,638,528 →
Application:
08/143,731 →
Data Processing System Having a Memory with Both a High Speed Operating Mode and a Low Power Operating Mode and Method Therefor
Patent:
5,737,566 →
Application:
08/169,103 →
Write Control for a Memory Using a Delay Locked Loop
Patent:
5,440,514 →
Application:
08/207,510 →
Synchronous Memory Having Parallel Output Data Paths
Patent:
5,402,389 →
Application:
08/207,513 →
Apparatus for Detecting a Signaling Channel During Scanning Including a Controlled Frequency Converter Circuit and a Controlled Filter Bandwidth, and a Method Therefor
Patent:
5,511,235 →
Application:
08/236,736 →
Dsp Co-Processor for Use on an Integrated Circuit That Performs Multiple Communication Tasks
Patent:
5,652,903 →
Application:
08/332,971 →
Integrated Circuit That Performs Multiple Communication Tasks
Patent:
5,621,800 →
Application:
08/333,152 →
Method and Apparatus for Extracting Digital Information from an Asynchronous Data Stream
Patent:
5,504,751 →
Application:
08/334,975 →
Transconductance Scaling Circuit and Method Responsive to a Received Digital Code Word for Use with an Operational Transconductance Circuit
Patent:
5,530,399 →
Application:
08/363,786 →
Method for Producing and Recovering a Data Stream for a Dmt Transceiver
Patent:
5,619,505 →
Application:
08/378,697 →
Method and Apparatus for Reducing Peak-to-Average Requirements in Multi-Tone Communication Circuits
Patent:
5,835,536 →
Application:
08/383,026 →
Method and Apparatus for Distributing Bus Loading in a Data Processing System
Patent:
5,638,520 →
Application:
08/414,473 →
Reset Configuration in a Data Processing System and Method Therefor
Patent:
5,623,687 →
Application:
08/494,664 →
Method and Apparatus for Bursting Operand Transfers During Dynamic Bus Sizing
Patent:
5,689,659 →
Application:
08/550,043 →
Data Processor with Flexible Data Encryption
Patent:
5,892,826 →
Application:
08/593,987 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent:
5,787,291 →
Application:
08/598,833 →
Flexible Asymmetrical Digital Subscriber Line (Adsl) Receiver, Central Office Using Same, and Method Therefor
Patent:
5,742,527 →
Application:
08/616,818 →
Flexible Asymmetrical Digital Subscriber Line Adsl) Transmitter, Remote Terminal Using Same, and Method Therefor
Patent:
5,781,728 →
Application:
08/616,819 →
Transfer Rate Controller and Method of Operation
Patent:
5,889,763 →
Application:
08/658,046 →
Method and Apparatus for Performing Different Cache Replacement Algorithms for Flush and Non-Flush Operations in Response to a Cache Flush Control Bit Register
Patent:
5,778,432 →
Application:
08/674,050 →
Apparatus and Method for Clock Recovery in a Communication System
Patent:
5,898,744 →
Application:
08/722,433 →
Interface for an Asymmetric Digital Subscriber Line Transceiver
Patent:
5,825,768 →
Application:
08/723,437 →
Method and Apparatus for Frequency Domain Ripple Compensation for a Communications Transmitter
Patent:
5,825,826 →
Application:
08/724,097 →
Method and Apparatus for Controlling Bus Arbitration in a Data Processing System
Patent:
5,894,562 →
Application:
08/738,515 →
Single-Chip Software Configurable Transceiver for Asymmetric Communication System
Patent:
5,909,463 →
Application:
08/741,634 →
Transfer Layer of the Atm Type and Method for Operating a Transfer Switch
Patent:
5,892,755 →
Application:
08/768,013 →
Asymmetrical Digital Subscriber Line (Adsl) Block Encoder Circuit and Method of Operation
Patent:
5,883,907 →
Application:
08/848,902 →
Modular Switch Element for Shared Memory Switch Fabric
Patent:
5,859,849 →
Application:
08/851,731 →
Atm Line Card and Method for Transferring Connection Memory Data
Patent:
5,923,658 →
Application:
08/856,835 →
Method and Apparatus for Controlling a Memory Device in a Page Mode
Patent:
5,848,025 →
Application:
08/885,434 →
Method for Digital Signal Processing, Dsp, Mobile Communication and Audio-Device
Patent:
6,145,070 →
Application:
08/912,243 →
Method and Appartus for Suspending a Program/Erase Operation in a Flash Memory
Patent:
5,822,244 →
Application:
08/936,373 →
Paged Memory Data Processing System with Overlaid Memory Control Registers
Patent:
6,058,463 →
Application:
09/009,509 →
Apparatus and Method for Transmitting Data
Patent:
6,167,059 →
Application:
09/013,048 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent:
5,951,688 →
Application:
09/024,607 →
Sigma-Delta Modulator and Method for Digitizing a Signal
Patent:
6,087,969 →
Application:
09/067,147 →
Customizable Instruction Set Processor with Non-Configurable/Configurable Decoding Units and Non-Configurable/Configuravble Execution Units
Patent:
6,138,229 →
Application:
09/086,741 →
Line Driver Circuit with Reduced Power Consumption
Patent:
6,100,717 →
Application:
09/174,148 →
Communication System with Physical Interface and Communication Controller, and Method
Patent:
6,574,228 →
Application:
09/241,195 →
Electronic Apparatus and Method for Receiving Noisy Signals
Patent:
6,529,567 →
Application:
09/265,221 →
Circuit and Method of Controlling Cache Memory
Patent:
6,279,083 →
Application:
09/275,617 →
High Performance Communication Controller for Processing High Speed Data Streams Wherein Execution of a Task Can Be Skipped If Involves Fetching Information from External Memory Bank
Patent:
6,473,808 →
Application:
09/285,519 →
Fast Training of Equalizers in Discrete Multi-Tone (Dmt) Systems
Patent:
6,535,552 →
Application:
09/314,587 →
Low Power Data Processing System for Interfacing with an External Device and Method Therefor
Patent:
6,119,240 →
Application:
09/321,389 →
Communication System with Communication Controller and Multiple Physical Interfaces, and Method
Patent:
6,490,283 →
Application:
09/348,101 →
Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
Patent:
6,892,339 →
Application:
09/398,707 →
High frequency detection circuit and method
Patent:
6,259,279 →
Application:
09/493,585 →
Reassembly Unit and a Method Thereof
Patent:
6,665,298 →
Application:
09/494,601 →
Method for digital signal processing,dsp,mobile communication and audio-device
Patent:
6,282,623 →
Application:
09/497,986 →
Method and Apparatus for Performing Hierarchical Address Translation
Patent:
6,711,661 →
Application:
09/606,995 →
Single Instruction for Multiple Loops
Method and Circuit for Forming an Atm Cell
Memory Interface Protocol Using Two Addressing Modes and Method of Operation
Method and Apparatus for Managing Multicast Data on an Ip Subnet
Memory Having a Synchronous Controller and Asynchronous Array and Method Thereof
Patent:
6,490,225 →
Application:
10/004,721 →
Simple Encoding/Decoding Technique for Code Position Modulation
Method and System for Accessing Memory Devices
Method and Apparatus for Generating a Pulse Width Modulated Signal
System and Apparatus for Reducing the Effects of Circuit Mismatch in Analog-to-Digital Converters
Data Transfer Unit with Support for Multiple Coherency Granules
Passive Response Communication System
Performance Monitor and Method Therefor
Continuous-Time Sigma-Delta Modulator with Discrete Time Common-Mode Feedback
Patent:
6,697,001 →
Application:
10/324,684 →
Passive Communication Device and Passive Access Control System
I/Q Mismatch Compensation in an Ofdm Receiver in Presence of Frequency Offset
Arrangement and Method for Connecting a Processing Node in a Distribution System
A Multimode Decoder
Programmable Phase Mapping and Phase Rotation Modulator and Method
Method and Circuitry for Controlling Supply Voltage in a Data Processing System
Data Processing System Having a Serial Data Controller
Method and Apparatus for Processing a Frequency Modulated (Fm) Signal Using an Adaptive Equalizer
Method and Apparatus for Complex Cascade Sigma-Delta Modulation and Single-Sideband Analog-to-Digital Conversion
High Resolution Pulse Width Modulator
Fully Programmable Phase Locked Loop
Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
Methods and Apparatus for Bit Synchronizing Data Transferred Across a Multi-Pin Asynchronous Serial Interface
Dc Offset Correction System for a Receiver with Baseband Gain Control
One Time Programmable Memory and Method of Operation
System and Method for Wireless Broadband Context Switching
Convolution Operation in a Multi-Mode Wireless Processing System
Modulation Detection in a Saic Operational Environment
Priority Queuing of Frames in a Tdma Network
Dynamic Switching Between Maximum Likelihood Sequence Estimation (Mlse) and Linear Equalizer for Single Antenna Interference Cancellation (Saic) in a Global System for Mobile Communications (Gsm) System
Media-Independent Handover (Mih) Method Featuring a Simplified Beacon
Selective Transaction Request Processing at an Interconnect During a Lockout
Mitigation of Dc Distortion in Ofdm Receivers
System and Method for Implementing Acls Using Standard Lpm Engine
Lookup Table Array Compression and Indexing
Re-Configurable Impedance Matching and Harmonic Filter System
Continuous Time Noise Shaping Analog-to-Digital Converter
Data Stream Processing Method and System
Method and System for Decoding Data
Resource Allocation in Multi Data Stream Communication Link
System and Method for Reporting Cache Coherency State Retained Within a Cache Hierarchy of a Processing Node
Wireless Communication Device and Data Interface
Apparatus and Method for Controlling Voltage and Frequency
Methods and Apparatus for Round Trip Time Measurements
Methods and Apparatus for a Spread Spectrum Switching Regulator
Parallel Processing for Single Antenna Interference Cancellation
Joint De-Spreading and Frequency Correction Using a Correlator
Interprocessor Message Transmission via Coherency-Based Interconnect
System and Method for Receiving a Multiple Format Wireless Signal
System and Method for Transmitting a Multiple Format Wireless Signal
System and Method for Monitoring Network Traffic
Adaptive Equalizer for Communication Channels
Discrete Dithered Frequency Pulse Width Modulation
Method of Transitioning Between Active Mode and Power-Down Mode in Processor Based System
Discrete Multi-Tone (Dmt) System and Method That Communicates a Data Pump Data Stream Between a General Purpose Cpu and a Dsp via a Buffering Scheme
Cache Locking Device and Methods Thereof
Digital Audio Amplifiers, Electronic Systems, and Methods
Gain Control Methods for Wireless Devices and Transmitters
Gmsk-Receiver with Interference Cancellation
Initiation of High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
Data Arbitration on a Bus to Determine an Extreme Value
Techniques for Compressing Differential Samples of Bandwidth-Limited Data to Reduce Bandwidth and Power Consumption by an Interface
Wireless Communication Unit, Integrated Circuit and Biasing Therefor
Power Amplifiers Having Improved Startup Linearization and Related Operating Methods
Groups of Serially Coupled Processor Cores Propagating Memory Write Packet While Maintaining Coherency Within Each Group Towards a Switch Coupled to Memory Partitions
Method for Managing Under-Runs and a Device Having Under-Run Management Capabilities
Gain Control Methods for Wireless Devices and Transmitters
Systems and Methods for Adjusting Headroom of a Power Amplifier
Communication Steering for Use in a Multi-Master Shared Resource System
Power Amplifier with Pre-Distorter
Method for Transmitting Data from Multiple Clock Domains and a Device Having Data Transmission Capabilities
Method for Processing Information Fragments and a Device Having Information Fragment Processing Capabilities
Spread Spectrum Pulse Width Modulation Method and Apparatus
Manipulating Data Streams in Data Stream Processors
Coherency Groups of Serially Coupled Processing Cores Propagating Coherency Information Containing Write Packet to Memory
High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
High Speed Overlay Mode for Burst Data and Real Time Streaming (Audio) Applications
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040928 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040925 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →