System and method for reporting cache coherency state retained within a cache hierarchy of a processing node
View Patent ↗A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to receiving a memory transaction request associated with the coherency granule at the processor. A coherency state of the coherency granule retained at the processor subsequent to the memory transaction request is determined based on the plurality of coherency states and an indicator representative of the coherency state of the coherency granule retained at the processor is provided for receipt by a cache coherency directory.
1. A method comprising:
determining, at a first processor of a multiple-processor system, a coherency state of a coherency granule for each of a plurality of caches of the first processor to generate a first plurality of coherency states in response to receiving a memory transaction request associated with the coherency granule at the first processor;
determining, at the first processor, a first coherency state of the coherency granule based on the first plurality of coherency states, the first coherency state representative of a coherency state retained at the first processor subsequent to the memory transaction request; and
providing an indicator representative of the first coherency state for receipt by a cache coherency directory.
2. The method of claim 1 , further comprising:
updating the cache coherency directory based on the indicator of the first coherency state.
3. The method of claim 1 , wherein determining the coherency state of the coherency granule for each cache of the plurality of caches comprises:
snooping each cache of the plurality of caches to determine the coherency state of the coherency granule for the cache; and
storing an indicator of the coherency state of the coherency granule for each cache of the plurality of caches in a corresponding storage location.
4. The method of claim 1 , wherein determining the first coherency state comprises:
determining a select coherency state of the first plurality of coherency states having the most restrictive coherency state of the first plurality of coherency states; and
providing the select coherency state as the first coherency state.
5. The method of claim 4 , wherein each of a plurality of potential coherency states is associated with a distinct value corresponding to a relative restrictiveness of the coherency state.
6. The method of claim 1 , further comprising:
determining, at a second processor of the multiple-processor system, a coherency state of a coherency granule for each of a plurality of caches of the second processor to generate a second plurality of coherency states in response to receiving the memory transaction request;
determining a second coherency state of the coherency granule based on the second plurality of coherency states, the second coherency state representative of a coherency state retained at the second processor subsequent to the memory transaction request; and
providing an indicator of the second coherency state for receipt by the cache coherency directory.
7. The method of claim 1 , further comprising:
performing a cache action in response to receiving the memory transaction request; and
providing an indicator representative of a compliance with a coherency requirement of the memory transaction request for receipt by the cache coherency directory.
8. The method of claim 7 , further comprising:
updating the cache coherency directory based on the indicator representative of the compliance with the coherency requirement.
9. A method comprising:
receiving, at a first processor of a multiple-processor system, a memory transaction request associated with a coherency granule;
processing the memory transaction request at the first processor;
determining a compliance with a coherency requirement of the memory transaction request;
determining a first coherency state of the coherency granule, the first coherency state representative of a coherency state retained at the first processor subsequent to the memory transaction request; and
providing a first indicator representative of the compliance with the coherency requirement and a second indicator representative of the first coherency state for receipt by a cache coherency directory associated with the multiple-processor system.
10. The method of claim 9 , further comprising:
updating the cache coherency directory based on the first indicator and the second indicator.
11. The method of claim 9 , wherein determining the coherency state comprises:
snooping each cache of a plurality of caches of the first processor to determine the coherency state of the coherency granule for the cache;
determining a select coherency state having the most restrictive coherency state of the coherency states of the coherency granule for the plurality of caches; and
providing the select coherency state as the first coherency state.
12. The method of claim 11 , wherein each of a plurality of potential coherency states is associated with a distinct value corresponding to a relative restrictiveness of the coherency state and wherein determining the select coherency state having the most restrictive coherency state comprises selecting the select coherency state based on a value associated with each corresponding coherency state.
13. The method of claim 9 , further comprising:
receiving, at a second processor of the multiple-processor system, the memory transaction request;
processing the memory transaction request at the second processor;
determining a compliance with the coherency requirement of the memory transaction request for the second processor;
determining a second coherency state, the second coherency state representative of a coherency state of the coherency granule retained at the second processor subsequent to the memory transaction; and
providing a third indicator representative of the compliance with the coherency requirement for the second processor and a fourth indicator representative of the second coherency state for receipt by the cache coherency directory.
14. A system comprising:
a first processor comprising:
a port configured to couple to a transaction management module associated with a plurality of processors;
a processor core;
a plurality of caches; and
a coherency management module configured to provide a first indicator representative of a first coherency state, first coherency state representative of a coherency state of a coherency granule retained at the plurality of caches subsequent to a processing of a memory transaction request associated with the coherency granule.
15. The system of claim 14 , wherein the port is configured to receive the memory transaction request via the transaction management module.
16. The system of claim 14 , wherein the coherency management module is configured to:
snoop each cache of the plurality of caches to generate a plurality of coherency states; and
determine a select coherency state of the plurality of coherency states having the most restrictive coherency state of the plurality of coherency states, wherein the select coherency state represents a cache coherency state of the coherency granule retained by the first processor subsequent to the memory transaction.
17. The system of claim 14 , further comprising:
a cache coherency directory coupled to the transaction management module, wherein the cache coherency directory is configured to update coherency information for the coherency module based on the first indicator.
18. The system of claim 14 , wherein the coherency management module is configured to provide a second indicator representative of a compliance with a coherency requirement of the memory transaction request.
19. The system of claim 18 , further comprising:
a cache coherency directory having an input to receive the first indicator and the second indicator, and wherein the cache coherency directory is configured to update stored coherency information associated with the coherency granule for the multiple-processor system based on the first indicator and the second indicator.
20. The system of claim 14 , further comprising:
a second processor comprising:
a port configured to couple to the transaction management module;
a processor core;
a plurality of caches; and
a coherency management module configured to provide a second indicator representative of a second coherency state, the second coherency state representative of a coherency state of the coherency granule retained at the plurality of caches of the second processor subsequent to a processing of the memory transaction request.