Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
View Patent ↗A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
1. A method for operating an information system within an integrated circuit, the method comprising:
generating a first packet of information by a first processor core of a multi processor core circuit of the integrated circuit, wherein the first packet of information is directed to a first partition of a memory;
propagating the first packet of information from the first processor core to a second processor core, wherein the first processor core and the second processor core are in a first coherency group;
propagating the first packet of information from the second processor core to a packet switch;
propagating the first packet of information through the packet switch to the first partition of the memory;
maintaining coherency among the first partition of the memory, the first processor core, and the second processor core;
generating a second packet of information by a third processor core of the multi processor core circuit of the integrated circuit, wherein the second packet of information is directed to a second partition of the memory;
propagating the second packet of information from the third processor core to a fourth processor core, wherein the third processor core and the fourth processor core are in a second coherency group;
propagating the second packet of information from the fourth processor core to a packet switch;
propagating the second packet of information through the packet switch to the second partition of the memory; and
maintaining coherency among the second partition of the memory, the third processor core, and the fourth processor core.
2. The method of claim 1 , wherein the step of maintaining coherency among the first partition of the memory, the first processor core, and the second processor core comprises:
providing write coherency information of the first packet to the second processor core, wherein the second processor core uses the write coherency information to determine if the first packet is modifying data in the memory at a location that is cached in the second processor core.
3. The method of claim 2 further comprising:
transmitting the write coherency information by the second processor core to a fifth processor core of the multi processor core circuit, wherein the fifth processor core is in the first coherency group and uses the write coherency information to determine if the first packet is modifying data in the memory at a location that is cached in the fifth processor core.
4. The method of claim 1 wherein:
the third processor core and the fourth processor core do not receive write coherency information of the first packet.
5. The method of claim 1 wherein the first partition and the second partition have non overlapping addresses.
6. The method of claim 1 further comprising:
writing data of the first packet of information to a location in the first partition of the memory, wherein an address of the location is indicated in the first packet of information.
7. The method of claim 1 wherein the propagating the first packet of information includes propagating the first packet by a packet based protocol having ordered packets that support flow control and multiple prioritized transactions.