IP Library Granted Patent US 7,865,897
Granted Patent B2
US 7,865,897 · App. 11/347,103 · Granted Jan 4, 2011

Selective transaction request processing at an interconnect during a lockout

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Quick Facts
Patent No.
US 7,865,897
App. No.
11/347,103
Granted
Jan 4, 2011
Kind
B2
Abstract

A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

Claims (50)

1. A method comprising:

receiving, at an interconnect of an integrated circuit device, a first transaction request from a first requesting module of the integrated circuit device, the first transaction request including a request to utilize at least one resource accessible via the interconnect;

accessing, at the interconnect, an entry of an interferences table associated with the first transaction request to determine potential interferences expected to occur as a result of a utilization of the at least one resource by the first requesting module, the entry including data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module;

initiating processing of the first transaction request at the interconnect; and

authorizing processing of a second transaction request from a second requesting module of the integrated circuit device during the processing of the first transaction request responsive to determining the second requesting module is represented in the first set.

2. The method of claim 1 , wherein the request to utilize at least one resource comprises a lockout request.

3. The method of claim 2 , wherein the entry of the interferences table is identified based on a transaction identifier associated with the first transaction request.

4. The method of claim 1 , wherein the entry comprises a plurality of bit positions, each bit position associated with a corresponding one of a plurality of requesting modules and having one of a first value or a second value, the first value indicating that the corresponding requesting module is expected to interfere with the utilization of the at least one resource by the first requesting module and the second value indicating the corresponding requesting module is not expected to interfere with the utilization of the at least one resource by the first requesting module.

5. The method of claim 4 , wherein the request to utilize at least one resource comprises a lockout request.

6. The method of claim 1 , wherein the entry further includes data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module.

7. The method of claim 6 , wherein:

processing of the second transaction request is authorized when the first set includes the second requesting module; and

processing of the second transaction request is denied when the second set includes the second requesting module.

8. The method of claim 1 , wherein the entry of the interferences table is identified based on a transaction identifier associated with the first transaction request.

9. The method of claim 1 , wherein:

processing of the second transaction request is authorized when the second transaction request is not expected to interfere with the utilization of the at least one resource by the first requesting module; and

processing of the second transaction request is denied when the second transaction request is expected to interfere with the utilization of the at least one resource by the first requesting module.

10. A method comprising:

initiating, at a first time, processing of a first transaction request from a first requesting module of an integrated circuit device at an interconnect of the integrated circuit device;

receiving, at a second time subsequent to the first time, a second transaction request from a second requesting module of the integrated circuit device;

accessing, at the interconnect, an entry of a table based on transaction information associated with the first transaction request so as to determine whether the second transaction request is permitted to be processed at the interconnect concurrently with the first transaction request, the entry including data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module and data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module;

initiating, at a third time subsequent to the second time, processing of the second transaction request at the interconnect when it is determined that the second transaction request is permitted to be processed concurrently with the first transaction request; and

terminating, at a fourth time subsequent to the third time, the processing of the first transaction request.

11. The method of claim 10 , wherein:

accessing the table based on the transaction identifier so as to determine whether the second transaction request is permitted to be processed includes determining whether the second requesting module is represented in the first set or represented in the second set.

12. The method of claim 11 , wherein:

processing of the second transaction request is initiated at the interconnect when the second requesting module is represented in the first set; and

processing of the second transaction request is denied at the interconnect when the second requesting module is represented in the second set.

13. The method of claim 11 , further comprising:

denying processing of the second transaction request at the interconnect when it is determined that the second transaction request is not permitted to be processed concurrently with the first transaction request.

14. The method of claim 10 , further comprising:

denying processing of the second transaction request at the interconnect when it is determined that the second transaction request is not permitted to be processed concurrently with the first transaction request.

15. The method of claim 14 , wherein:

accessing the table based on the transaction identifier so as to determine whether the second transaction request is permitted to be processed includes determining whether the second requesting module is represented in the first set or represented in the second set.

16. The method of claim 10 , further comprising:

receiving, at a fifth time subsequent to the first time and prior to the third time, a third transaction request from a third requesting module of the integrated circuit device;

determining whether the third transaction request is permitted to be processed at the interconnect concurrently with the first transaction request based on the access of the table; and

initiating, at a sixth time subsequent to the fifth time and prior to the fourth time, processing of the third transaction request at the interconnect when it is determined that the third transaction request is permitted to be processed concurrently with the first transaction request.

17. The method of claim 10 , wherein the first transaction request comprises a lockout request.

18. An integrated circuit device comprising:

an inferences table;

an interconnect operably coupled to a first requesting module, a second requesting module and a plurality of resources, the interconnect comprising:

means for receiving a first transaction request from the first requesting module, the first transaction request including a request to utilize at least one resource of the plurality of resources;

means for accessing an entry of the interferences table to determine potential interferences expected to occur as a result of a utilization of the at least one resource by the first requesting module, the entry comprising data indicating that transaction requests from a first set of one or more identified requesting modules are not expected to interfere with the utilization of the at least one resource by the first requesting module and data indicating that transaction requests from a second set of one or more identified requesting modules are expected to interfere with the utilization of the at least one resource by the first requesting module;

means for initiating processing of the first transaction request at the interconnect; and

means for authorizing processing of a second transaction request from the second requesting module during the processing of the first transaction request responsive to determining the second requesting module is represented in the first set.

19. The integrated circuit device of claim 18 , wherein the entry comprises a plurality of bit positions, each bit position associated with a corresponding one of a plurality of requesting modules and having one of a first value or a second value, the first value indicating that the corresponding requesting module is expected to interfere with the utilization of the at least one resource by the first requesting module and the second value indicating the corresponding requesting module is not expected to interfere with the utilization of the at least one resource by the first requesting module.

20. The integrated circuit device of claim 18 , wherein:

the interconnect authorizes processing of the second transaction request when the second transaction request is not expected to interfere with the utilization of the at least one resource by the first requesting module; and

the interconnect denies processing of the second transaction request when the second transaction request is expected to interfere with the utilization of the at least one resource by the first requesting module.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZENITH INVESTMENTS, LLC
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →