Method of transitioning between active mode and power-down mode in processor based system
View Patent ↗A method of transitioning between an active mode and a power-down mode in a processor-based system includes saving a state of the active mode, detecting the occurrence of one or more interrupt events during a transition between the active mode and the power-down mode, and responding to the detected interrupt events.
1. A method of transitioning between an active mode and a power-down mode in a processor-based system through one or more intermediate states, the method comprising:
saving a state of the active mode, including saving the state of a set of first registers of the processor-based system, and saving the state of a set of read-only registers of the processor-based system;
detecting occurrence of one or more interrupt events during a transition between the active mode and the power-down mode;
responding to a first set of interrupt events from amongst the one or more interrupt events, wherein the first set of interrupt events occur during the transition from the active mode to the one or more intermediate states; and
restoring the state of the set of read only registers, wherein said restoring the state of the set of read-only registers comprises implementing a priority scheme for a status-event write operation and a software-restore write operation, and wherein the priority scheme is based on a functionality of the set of read-only registers.
2. The method of transitioning between an active mode and a power-down mode of claim 1 , wherein saving the state of the set of read-only registers comprises saving the state of a plurality of cache state registers when the plurality of cache state registers are to be powered off and an associated cache memory array remains powered up.
3. The method of transitioning between an active mode and a power-down mode of claim 1 , wherein the processor-based system includes a cache module having a plurality of cache arrays and associated cache state registers, and the step of saving the state of the active mode further comprises:
performing at least one of saving the state of the cache state registers when the plurality of cache arrays remain powered up and a remainder of the cache module is powered off and flushing the cache arrays when the entire cache module is to be powered off.
4. The method of transitioning between an active mode and a power-down mode of claim 1 , wherein responding to the first set of interrupt events comprises performing at least one of restarting the transition from the active mode to the power-down mode, restarting the transition from the active mode to the power-down mode after a predefined time interval, aborting the transition from the active mode to the power-down mode, and sending a wake-up signal to the processor-based system, upon serving the first set of interrupt events.
5. The method of transitioning between an active mode and a power-down mode of claim 4 , wherein aborting the transition comprises aborting the transition to the power-down mode based on the occurrence of an interrupt event of the first set of interrupt events, wherein the interrupt event occurs during flushing out a plurality of pipelines of the processor-based system.
6. The method of transitioning between an active mode and a power-down mode of claim 4 , wherein aborting the transition comprises aborting the transition to the power-down mode based on the occurrence of an interrupt event of the first set of interrupt events, wherein the interrupt event occurs during sending a power-down signal.
7. The method of transitioning between an active mode and a power-down mode of claim 1 , further comprising:
flushing a plurality of pipelines of the processor-based system;
sending a power-down signal after the flushing of the plurality of pipelines, wherein the power-down signal is sent by a central processing unit (CPU) of the processor-based system to a power-control module of the processor-based system; and
powering off the CPU of the processor-based system in response to the power-down signal.
8. The method of transitioning between an active mode and a power-down mode of claim 1 , further comprising masking a second set of interrupt events from amongst the one or more interrupt events, wherein the second set of interrupt events occur during one of the transition from the one or more intermediate states to the power-down mode and the transition from the power-down mode to the active mode.
9. The method of transitioning between an active mode and a power-down mode of claim 1 , wherein the transition between the active mode and the power-down mode comprises transition from the power-down mode to the active mode of the processor-based system.
10. The method of transitioning between an active mode and a power-down mode of claim 9 , wherein the transition from the power-down mode to the active mode comprises:
detecting at least one wake-up event;
initiating a wake-up process;
restoring the processor-based system to reach the active mode; and
unmasking a second set of interrupt events upon attaining the active mode.
11. The method of transitioning between an active mode and a power-down mode of claim 10 , wherein the step of restoring the processor-based system comprises:
restoring the state of a set of first registers;
restoring the state of a set of read-only registers by sending a write-control signal to enable a software-restore write operation that restores the state of the set of read-only registers; and
restoring the state of a plurality of cache state registers, wherein the plurality of cache state registers are powered off during the power-down mode and an associated cache memory array remains powered up.
12. A method of transitioning between an active mode and a power-down mode in a processor-based system through one or more intermediate states, comprising:
saving a state of the active mode;
detecting occurrence of one or more interrupt events during a transition between the active mode and the power-down mode;
responding to a first set of interrupt events from amongst the one or more interrupt events, wherein the first set of interrupt events occur during the transition from the active mode to the one or more intermediate states; and
transitioning from the active mode to the power-down mode when a time during which the processor-based system has to remain in the power-down mode is greater than a break-even time, wherein the break-even time is a time for which the processor-based system remains in the power-down mode to save power.