Techniques for compressing differential samples of bandwidth-limited data to reduce bandwidth and power consumption by an interface
View Patent ↗Techniques and technologies are provided for compressing differential samples of bandwidth-limited data and coding the compressed differential samples to reduce bandwidth and power consumption when communicating bandwidth-limited data over a serial interface which couples one integrated circuit to another integrated circuit.
1. A method of processing a bandwidth-limited data stream which comprises a number (n) of bandwidth-limited data samples (1 . . . n), the method comprising:
receiving the bandwidth-limited data samples (1 . . . n), wherein values of each of the bandwidth-limited data samples require at most a first number of bits (b) to represent;
performing at least one differentiation operation on each of the bandwidth-limited data samples to generate a number (n) of i th order differential samples corresponding to the bandwidth-limited data samples (1 . . . n);
selecting a number (p) of consecutive i th order differential samples, wherein p≦n;
determining whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits; and
compressing the number (p) of consecutive i th order differential samples by removing a third number of bits (b t ) from each of the number (p) of i th order differential samples to generate a number (p) of consecutive compressed-differential samples, wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits.
2. A method according to claim 1 , further comprising the steps of:
generating a specific compression bit code (bc t ) which indicates the number of bits (b t ) to be removed from each of the number (p) of consecutive i th order differential samples when values of each of the number (p) of consecutive i th order differential samples are representable using the second number (b−b t ) of bits that is less than the first number (b) of bits;
selecting the number (p) of consecutive i th order differential samples for framing and transmission instead of the number (p) of consecutive raw data samples;
generating a compressed frame comprising the number (p) of consecutive compressed-differential samples and the specific compression bit code (bc t ); and
transmitting the compressed frame over a serial interface.
3. A method according to claim 1 , wherein the bandwidth-limited data samples are received from a data source, and further comprising the steps of:
receiving the compressed frame at a data sink.
4. A method according to claim 1 , further comprising the steps of:
selecting a number (p) of consecutive ones of the bandwidth-limited data samples (1 . . . n) when a value of at least one of the number (p) of consecutive i th order differential samples is not representable using a second number (b−b t ) of bits that is less than the first number (b) of bits;
generating a default bit code (bc d ) which indicates that no bits are removed from the number (p) of bandwidth-limited data samples; and
generating a frame comprising the number (p) of consecutive bandwidth-limited data samples and the default bit code (bc d ).
5. A method according to claim 1 , wherein the step of determining whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits, comprises the steps of:
dynamically determining whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits such that values of each of the number (p) of i th order differential samples can be subsequently reduced by a number (b t ) of bits with respect to the first number (b) of bits required to represent corresponding values of each of a number (p) of the bandwidth-limited data samples.
6. A method according to claim 5 , wherein a plurality of threshold values (threshold — 1 . . . threshold_T) are provided such that when the values of each of the number (p) of consecutive i th order differential samples are less than a particular one of the threshold values (threshold — 1 . . . threshold_T), the number (p) of consecutive i th order differential samples can be represented with b−b t bits, where b is the number of bits used to represent the value of any of a number (p) of the bandwidth-limited data samples (1 . . . p) and b t is an integer number of bits to be trimmed from each of the number (p) of the bandwidth-limited data samples (1 . . . p), and wherein the step of dynamically determining, comprises the steps of:
comparing a value of each of the number (p) of consecutive i th order differential samples to a current threshold value (threshold — 1 ) of the plurality of threshold values (threshold — 1 . . . threshold_T); and
determining whether a value of each of the number (p) of consecutive i th order differential samples is less than the current threshold value to determine if each of the number (p) of consecutive i th order differential samples fits within the current threshold value (threshold — 1 . . . threshold_T) without any loss.
7. A method according to claim 6 , further comprising the steps of:
determining whether the current threshold value is a last threshold value (threshold_T) when one or more of the p consecutive i th order differential samples is greater than or equal to the current threshold value (threshold — 1 );
comparing the number (p) of consecutive i th order differential samples to a next current threshold value of the threshold values (threshold — 1 . . . threshold_T) when the current threshold value is not the last threshold value (threshold_T);
determining whether one or more of the number (p) of consecutive i th order differential samples is greater than or equal to the new current threshold value (threshold — 2 ), when it is determined that the current threshold value is not the last threshold value (threshold_T); and
determining whether the next current threshold value is the last threshold value (threshold_T) when one or more of the number (p) of consecutive i th order differential samples is greater than or equal to the new current threshold value (threshold — 2 ).
8. A method according to claim 1 , wherein the step of compressing the number (p) of consecutive i th order differential samples, comprises the steps of:
determining, based on the specific compression bit code (bc t ), the third number of bits (b t ) which are to be removed from each of the number (p) of consecutive i th order differential samples; and
removing the third number of bits (b t ) from each of the number (p) of consecutive i th order differential samples to compress each of the number (p) of consecutive i th order differential samples and generate the number (p) of consecutive compressed-differential samples, wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits such that the second number (b−b t ) of bits required to represent each of the compressed-differential samples is reduced in comparison to the first number (b) of bits required to represent a value of each of the number (p) of consecutive i th order differential samples and to represent a value of each of the bandwidth-limited data sample.
9. A method according to claim 1 , wherein the bandwidth-limited data samples (1 . . . n) comprise:
bandwidth-limited I/Q data samples (1 . . . n).
10. A processor module designed to process a bandwidth-limited data stream which comprises a number (n) of bandwidth-limited data samples (1 . . . n), the processor module comprising:
a differential computation module designed to perform at least one differentiation operation on each of the bandwidth-limited data samples (1 . . . n) to generate a number (n) of i th order differential samples corresponding to the bandwidth-limited data samples (1 . . . n), wherein values of each of the number (n) of bandwidth-limited data samples (1 . . . n) require at most a first number of bits (b) to represent;
a dynamic compression and coding module, comprising:
a threshold comparator module designed to select a number (p) of consecutive i th order differential samples, wherein p≦n, and to determine whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits; and
a compression module designed to compress the number (p) of consecutive i th order differential samples by removing a third number of bits (b t ) from each of the number (p) of i th order differential samples to generate a number (p) of consecutive compressed-differential samples, wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits.
11. A processor module according to claim 10 , further comprising:
a bit code generator module designed to generate a specific compression bit code (bc t ) which indicates the number of bits (b t ) to be removed from each of the number (p) of consecutive i th order differential samples when values of each of the number (p) of consecutive i th order differential samples are representable using the second number (b−b t ) of bits that is less than the first number (b) of bits;
a first sample selector module designed to select the number (p) of consecutive i th order differential samples for framing and transmission instead of the number (p) of consecutive raw data samples; and
a framing module designed to generate a compressed frame comprising the number (p) of consecutive compressed-differential samples and the specific compression bit code (bc t ), and to transmit the compressed frame over a serial interface coupled to a data sink.
12. A processor module according to claim 11 , further comprising:
wherein the sample selector module is further designed to select a number (p) of consecutive ones of the bandwidth-limited data samples (1 . . . n) when a value of at least one of the number (p) of consecutive i th order differential samples is not representable using a second number (b−b t ) of bits that is less than the first number (b) of bits;
wherein the bit code generator module is further designed to generate a default bit code (bc d ) which indicates that no bits are removed from the number (p) of bandwidth-limited data samples; and
wherein the framing module is further designed to generate a frame comprising the number (p) of consecutive bandwidth-limited data samples and the default bit code (bc d ).
13. A processor module according to claim 10 , wherein the threshold comparator module is further designed to: dynamically determine whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits such that values of each of the number (p) of i th order differential samples can be subsequently reduced by a number (b t ) of bits with respect to the first number (b) of bits required to represent corresponding values of each of a number (p) of the bandwidth-limited data samples.
14. A processor module according to claim 13 , wherein the threshold comparator module is further designed to:
receive a plurality of threshold values (threshold — 1 . . . threshold_T) such that when the values of each of the number (p) of consecutive i th order differential samples are less than a particular one of the threshold values (threshold — 1 . . . threshold_T), the number (p) of consecutive i th order differential samples can be represented with b−b t bits, where b is the number of bits used to represent the value of any of a number (p) of the bandwidth-limited data samples (1 . . . p) and b t is an integer number of bits to be trimmed from each of the number (p) of the bandwidth-limited data samples (1 . . . p); and
compare a value of each of the number (p) of consecutive i th order differential samples to a current threshold value (threshold — 1 ) of the plurality of threshold values (threshold — 1 . . . threshold_T), and determine whether a value of each of the number (p) of consecutive i th order differential samples is less than the current threshold value to determine if each of the number (p) of consecutive i th order differential samples fits within the current threshold value (threshold — 1 . . . threshold_T) without any loss.
15. A processor module according to claim 14 , wherein the threshold comparator module is further designed to:
determine whether the current threshold value is a last threshold value (threshold_T) when one or more of the p consecutive i th order differential samples is greater than or equal to the current threshold value (threshold — 1 );
compare the number (p) of consecutive i th order differential samples to a next current threshold value of the threshold values (threshold — 1 . . . threshold_T) when the current threshold value is not the last threshold value (threshold_T), and determine whether one or more of the number (p) of consecutive i th order differential samples is greater than or equal to the new current threshold value (threshold — 2 ) when it is determined that the current threshold value is not the last threshold value (threshold_T); and
determine whether the next current threshold value is the last threshold value (threshold_T) when one or more of the number (p) of consecutive i th order differential samples is greater than or equal to the new current threshold value (threshold — 2 ).
16. A processor module according to claim 10 , wherein the compression module designed to determine the third number of bits (b t ) which are to be removed from each of the number (p) of consecutive i th order differential samples based on the specific compression bit code (bc t ), and to remove the third number of bits (b t ) from each of the number (p) of consecutive i th order differential samples to compress each of the number (p) of consecutive i th order differential samples and generate the number (p) of consecutive compressed-differential samples,
wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits such that the second number (b−b t ) of bits required to represent each of the compressed-differential samples is reduced in comparison to the first number (b) of bits required to represent a value of each of the number (p) of consecutive i th order differential samples and to represent a value of each of the bandwidth-limited data sample.
17. A processor module according to claim 10 , wherein the bandwidth-limited data samples (1 . . . n) comprise: bandwidth-limited I/Q data samples (1 . . . n).
18. A system, comprising:
a data source integrated circuit designed to generate a bandwidth-limited data stream which comprises a number (n) of bandwidth-limited data samples (1 . . . n);
a data sink integrated circuit; and
a serial interface which couples the data source integrated circuit to the data sink integrated circuit,
wherein one of the data source integrated circuit and the serial interface, comprise:
a processor module designed to process the number (n) of bandwidth-limited data samples (1 . . . n), the processor module comprising:
a differential computation module designed to perform at least one differentiation operation on each of the bandwidth-limited data samples (1 . . . n) to generate a number (n) of i th order differential samples corresponding to the bandwidth-limited data samples (1 . . . n), wherein values of each of the number (n) of bandwidth-limited data samples (1 . . . n) require at most a first number of bits (b) to represent;
a dynamic compression and coding module, comprising:
a threshold comparator module designed to select a number (p) of consecutive i th order differential samples, wherein p≦n, and to determine whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits; and
a compression module designed to compress the number (p) of consecutive i th order differential samples by removing a third number of bits (b t ) from each of the number (p) of i th order differential samples to generate a number (p) of consecutive compressed-differential samples, wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits.
19. A system according to claim 18 , wherein the serial interface comprises:
an asynchronous serial interface which complies with the DigRF standard.
20. A system according to claim 18 , wherein the bandwidth-limited data samples (1 . . . n) comprise: bandwidth-limited I/Q data samples (1 . . . n), wherein the data source integrated circuit comprises a radio frequency integrated circuit, and wherein the data sink integrated circuit comprises a baseband integrated circuit.
21. An apparatus, comprising:
a radio frequency integrated circuit designed to receive a downlink RF signal and to generate, based on the downlink RF signal, a bandwidth-limited data stream which comprises a number (n) of bandwidth-limited I/Q data samples (1 . . . n);
a baseband integrated circuit; and
a serial interface which couples the baseband integrated circuit to the radio frequency integrated circuit, wherein one of the radio frequency integrated circuit and the serial interface, comprise:
a differential computation module designed to perform at least one differentiation operation on each of the bandwidth-limited I/Q data samples (1 . . . n) to generate a number (n) of i th order differential samples corresponding to the bandwidth-limited I/Q data samples (1 . . . n), wherein values of each of the number (n) of bandwidth-limited I/Q data samples (1 . . . n) require at most a first number of bits (b) to represent;
a dynamic compression and coding module, comprising:
a threshold comparator module designed to select a number (p) of consecutive i th order differential samples, wherein p≦n, and to determine whether each of the values of the number (p) of consecutive i th order differential samples is representable using a second number (b−b t ) of bits that is less than the first number (b) of bits; and
a compression module designed to compress the number (p) of consecutive i th order differential samples by removing a third number of bits (b t ) from each of the number (p) of i th order differential samples to generate a number (p) of consecutive compressed-differential samples, wherein a value of each of said compressed-differential samples is representable using at most the second number (b−b t ) of bits.