Patent Assignment
Reel/Frame 037354/0688
Patent Release
Recorded: 2015-12-21
Pages: 16
Assignor
CITIBANK, N.A., AS COLLATERAL AGENT
Executed: 2015-12-07
Assignee
FREESCALE SEMICONDUCTOR, INC.
6501 WILLIAM CANNON DRIVE WEST, AUSTIN, TEXAS, 78735
Covered Properties
(201)
Process for Depositing a Layer of Material on a Substrate and a Plating System
Method of Accommodating Overlapping or Adjacent Networks
Low Leakage Local Oscillator System
Conversion Between Optical and Radio Frequency Signals
Keypad Signal Input Apparatus
Data Processing System Having Instruction Specifiers for Simd Register Operands and Method Thereof
Communication Receiver
Apparatus for Pulse Testing a Mram Device and Method Therefore
Digital Rate Converter
Multiple Burst Protocol Device Controller
Wireless Transceiver and Method of Operating the Same
Method and Apparatus Utilizing Monocrystalline Insulator
Memory Device with a Data Hold Latch
Interfacial Layer for Use with High K Dielectric Materials
Data Processing System with Bus Access Retraction
Multi-Chips Semiconductor Device Assemblies and Methods for Fabricating the Same
Semiconductor Device Having Nitridated Oxide Layer and Method Therefor
Anti-Gate Leakage Programmable Capacitor
Method of Forming a Microelectronic Device
Enhancement Mode Transceiver and Switched Gain Amplifier Integrated Circuit
Method and Apparatus for Powering and Loading Software into a Battery-Less Electronic Device
Dynamic Gain and Phase Compensation for Power Amplifier Load Switching
Methods and Apparatus for Extending Semiconductor Chip Testing with Boundary Scan Registers
Semiconductor Package and Method for Forming the Same
Method of Making Planar Double Gate Silicon-on-Insulator Structures
Semiconductor Device and Method of Manufacture
Substrate Contact for a Capped Mems and Method of Making the Substrate Contact at the Wafer Level
Chemical Die Singulation Technique
Mram Embedded Smart Power Integrated Circuits
Baseband Rc Filter Pole and on-Chip Current Tracking System
Method of Fabricating a Nonvolatile Storage Array with Continuous Control Gate Employing Hot Carrier Injection Programming
Method of Forming a Finfet Structure
Nonvolatile Memory Cell Programming
Analog Signal Separator for Uwb Versus Narrowband Signals
Finfet Structure with Contacts
Low Noise Reference Oscillator with Fast Start-Up
Low Voltage Low Power Class a/B Output Stage
Method for Packaging a Semiconductor Device
Overcurrent Protection Circuit and Dc Power Supply
Esd Protection for Passive Integrated Devices
Method of Forming Device Having a Raised Extension Region
Charge-Free Layer by Layer Etching of Dielectrics
Electronic Device and Method for Operating a Memory Circuit
Method of Forming a Semiconductor Device with Decreased Undercutting of Semiconductor Material
Memory Cell Using a Dielectric Having Non-Uniform Thickness
Embedded Substrate Interconnect for Underside Contact to Source and Drain Regions
Method for Forming a Non-Volatile Memory and a Peripheral Device on a Semiconductor Substrate
Testing of Data Retention Latches in Circuit Devices
Slew Rate Control of a Charge Pump
System and Method for Operating a Feedback Network
Variable Interpolator for Non-Uniformly Sampled Signals and Method
Method and Apparatus for Controlling the Timing of a Communication Device
Integrator Current Matching
Deglitch Circuit
Method of Implementing Polishing Uniformity and Modifying Layout Data
Low Power Magnetoresistive Random Access Memory Elements
Stackable Molded Packages and Methods of Making the Same
Application:
11/968,873 →
Publication:
US 2008/0108179
Snoop Request Management in a Data Processing System
Micropad Formation for a Semiconductor
Methods for Forming Mos Capacitors
Removable Layer Manufacturing Method
Analog-To-Digital Converter Having Random Capacitor Assignment and Method Thereof
Patent:
7,535,391 →
Application:
11/969,982 →
Techniques for Compressing Differential Samples of Bandwidth-Limited Data to Reduce Bandwidth and Power Consumption by an Interface
Migfet Circuit with Esd Protection
Multiple Function Switching Regulator for Use in Mobile Electronic Devices
Application:
11/971,795 →
Publication:
US 2009/0174366
Esd Protection for Passive Integrated Devices
Spraying Apparatus, Method for Production Thereof and Use Thereof
Application:
11/989,116 →
Publication:
US 2009/0159722
Device and Method for Compensating for Voltage Drops
Compensation for Parasitic Coupling Between Rf or Microwave Transistors in the Same Package
Method of Forming a Continuous Layer of a First Metal Selectively on a Second Metal and an Integrated Circuit Formed from the Method
Ramping in Multimode Transmitters Using Primed Filters
Temperature Sensing Device
Voltage Regulator with Pass Transistors Carrying Different Ratios of the Total Load Current and Method of Operation Therefor
Switch Arrangement, Integrated Circuit, Activation System
Microphone Amplification Arrangement and Integrated Circuit Therefor
Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device
Multilayer Silicon Nitride Deposition for a Semiconductor Device
Method of Repeating Data Transmission Between Network Devices by Timing a First Predetermined Period After Previous First Data Transmission
Amplifier Having a Virtual Ground and Method Thereof
Load Insensitive Balanced Power Amplifier and Related Operating Method
Method and System for Estimating Power Consumption of Integrated Circuit Design
Microelectronic Refrigeration System and Method
Application:
12/013,812 →
Publication:
US 2009/0178436
Dynamic Allocation of Communication Resources in a Wireless System
Cache Using Pseudo Least Recently Used (Plru) Cache Replacement with Locking
Overcurrent Detection Circuit
Non-Volatile Memory with Reduced Charge Fluence
Capacitance Detection Circuit Including Voltage Compensation Function
Series regulator circuit
Application:
12/015,516 →
Publication:
US 2008/0191673
Method and Apparatus for Handling Shared Hardware and Software Debug Resource Events in a Data Processing System
Phase Change Memory Cell with Heater and Method Therefor
Method of Making a Phase Change Memory Cell Having a Silicide Heater in Conjunction with a Finfet.
Shared Resource Based Thread Scheduling with Affinity and/or Selectable Criteria
Tuning a Second Order Intercept Point of a Mixer in a Receiver
Battery-Less Electronic Device
Embedded Substrate Interconnect for Underside Contact to Source and Drain Regions
High Performance Cmos Radio Frequency Receiver
Regulator Circuit
State Retaining Power Gated Latch and Method Therefor
Method for Forming a Through Silicon via Layout
Circuit Having Logic State Retention During Power-Down and Method Therefor
Method of Removing Nanocrystals
Application:
12/022,800 →
Publication:
US 2012/0135596
Iii-V Mosfet Fabrication and Device
Electrostatic Discharge Protection
Device and Method for Adjusting an Impedance of an Output Driver of an Integrated Circuit
Patent:
7,969,181 →
Application:
12/025,030 →
Balun Transformer with Improved Harmonic Suppression
Encryption Apparatus with Diverse Key Retention Schemes
Method and System for Initializing an Interface Between Two Circuits of a Communication Device While a Processor of the First Circuit Is Inactive and Waking Up the Processor Thereafter
Analog-To-Digital Converter with Variable Gain and Method Thereof
High Bandwidth Cache-to-Processing Unit Communication in a Multiple Processor/Cache System
Self Regulating Biasing Circuit
Method for Generating Soft Decision Signal from Hard Decision Signal in a Receiver System
Separator with Transfer Tube Drainage
Configurable Receiver and a Method for Configuring a Receiver
Patent:
7,978,757 →
Application:
12/028,018 →
Split Channel Receiver with Very Low Second Order Intermodulation
Shielded Integrated Circuit Pad Structure
Method for Efficient Cqi Feedback
Integrated Circuit Die, Integrated Circuit Package, and Packaging Method
Peripheral Module Register Access Methods and Apparatus
Scalable Motion Search Ranges in Multiple Resolution Motion Estimation for Video Compression
Application:
12/032,394 →
Publication:
US 2009/0207915
Packaged Integrated Circuit with Enhanced Thermal Dissipation
Adjustable Pipeline in a Memory Circuit
Magnetic Tunnel Junction Device
Data Processor Device Having Trace Capabilities and Method
Data Processor Device Supporting Selectable Exceptions and Method Thereof
Data Processing Device and Method of Halting Exception Processing
Power on Detection Circuit
Multi-Channel Transistor Structure and Method of Making Thereof
Space Efficient Integrated Circuit with Passive Devices
Device Under Test De-Embedding
Resistor Triggered Electrostatic Discharge Protection
Method of Forming a Gate Dielectric
Method of Making a Vertical Phase Change Memory (Pcm) and a Pcm Device
Amplifier with Active Inductor
Circuit Device with at Least Partial Packaging and Method for Forming
Method of making a semiconductor device including a bridgeable material
Packaging an Integrated Circuit Die Using Compression Molding
Selective Postponement of Branch Target Buffer (Btb) Allocation
Metric for Selective Branch Target Buffer (Btb) Allocation
Method and Apparatus for Sharing Debug Resources
Method and Apparatus for Masking Debug Resources
Voltage Multiplier with Improved Efficiency
Fabrication of a Semiconductor Device with Stressor
Method of Programming a Memory Having Electrically Programmable Fuses
Pulse Circuit Using a Transmission Line
Microelectromechanical Systems Component and Method of Making Same
Method of Low Power Pll for Low Jitter Demanding Applications
Patent:
7,786,809 →
Application:
12/041,687 →
Automatic Calibration Lock Loop Circuit and Method Having Improved Lock Time
Lock Loop Circuit and Method Having Improved Lock Time
Scheme of Level Shifter Cell
Patent:
7,548,093 →
Application:
12/042,351 →
Method of Forming a Semiconductor Device Having a Stressed Electrode and Silicide Regions
Application:
12/043,372 →
Publication:
US 2009/0227099
System and Method for Reducing Power Consumption of Memory in an I/O Controller
Read Reference Technique with Current Degradation Protection
Qualification of Conditional Debug Instructions Based on Address
Pulse Width Modulation Wave Output Circuit
Change in Instruction Behavior Within Code Block Based on Program Action External Thereto
Application:
12/050,622 →
Publication:
US 2009/0240928
Power Amplifiers Having Improved Startup Linearization and Related Operating Methods
Techniques for Reducing Communication Errors in a Wireless Communication System
Schmitt Trigger Having Variable Hysteresis and Method Therefor
Application:
12/053,005 →
Publication:
US 2009/0237135
Computing Device with Entry Authentication into Trusted Execution Environment and Method Therefor
Channel Rank Updates in Multiple-Input Multiple-Output Communication Systems
Patent:
7,978,623 →
Application:
12/053,577 →
System and a Method for Providing an Output Clock Signal
Patent:
7,999,581 →
Application:
12/053,601 →
Lead Frame with Solder Flow Control
Low Leakage Current Amplifier
Application:
12/053,754 →
Publication:
US 2009/0237164
Selective Interconnect Transaction Control for Cache Coherency Maintenance
Setup and Hold Time Characterization Device and Method
Integrated Passive Device and Method with Low Cost Substrate
Application:
12/054,105 →
Publication:
US 2009/0236689
Techniques for Reducing Interference in a Communication System
Built-In Self-Calibration (Bisc) Technique for Regulation Circuits Used in Non-Volatile Memory
Led Driver with Dynamic Power Management
User Equipment Buffer Management in Multiple-Input Multiple-Output Communication Systems
Patent:
8,433,878 →
Application:
12/056,258 →
Quarter Duty Cycle Pulse Generator for Interleaved Switching Mixer
Techniques for Channel Sounding in a Wireless Communication System
Branch Target Buffer Addressing in a Data Processor
Application:
12/057,543 →
Publication:
US 2009/0249048
Hardware Managed Context Sensitive Interrupt Priority Level Control
Vehicle Outer Handle System
Techniques for Reducing Buffer Overflow in a Communication System
Method and Apparatus to Trace and Correlate Data Trace and Instruction Trace for Out-of-Order Processors
Hybrid Transistor Based Power Gating Switch Circuit and Method
Method and Apparatus for Mini Module Emi Shielding Evaluation
Semiconductor Through Silicon Vias of Variable Size and Method of Formation
Current Driver Suitable for Use in a Shared Bus Environment
Dual Gate Lateral Diffused Mos Transistor
Pore Sealing and Cleaning Porous Low Dielectric Constant Structures
Loop Gain Equalizer for Rf Power Amplifier
Handover Based on a Quality of Service Metric Obtained from a Mac Layer of a Received Signal
Application:
12/063,422 →
Publication:
US 2009/0154426
Field-Effect Semiconductor Device and Method of Forming the Same
Wireless Communication Unit, Integrated Circuit and Method for Biasing a Power Amplifier
Application:
12/063,425 →
Publication:
US 2010/0184389
Gate Electrode Silicidation Process
Method and a Computer Readable Medium for Performing Static Timing Analysis of a Design of an Integrated Circuit
Receiver and a Method for Channel Estimation
Power Saving in Signal Processing in Receivers
Method of Making an Integrated Circuit
Application:
12/067,583 →
Publication:
US 2008/0250374
Spin-Dependent Tunnelling Cell and Method of Formation Thereof
System and Method For Storing State Information
Application:
12/067,587 →
Publication:
US 2008/0256551
Controller and Method for Controlling an Ignition Coil
Device Having a Low Latency Single Port Memory Unit and a Method for Writing Multiple Data Segments to a Single Port Memory Unit
Application:
12/067,592 →
Publication:
US 2008/0235462
Integrated Circuit and a Method for Selecting a Voltage in an Integrated Circuit
Method and System for Performing Distance Measuring and Direction Finding Using Ultrawide Bandwitdh Transmissions
Metrology of Bilayer Photoresist Processes
Receiver Configurable in a Plurality of Modes
Adaptive Rate Control in a Communications System
Related Assignments
(25)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Assignment of Assignor's Interest
Oct 21, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033994/0655 →
Assignment of Assignor's Interest
Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
Assignment of Assignor's Interest
Jul 9, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 036084/0057 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Assignment of Assignor's Interest
Jan 25, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037567/0531 →
Assignment of Assignor's Interest
Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
Security Agreement Supplement
Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
Supplement to the Security Agreement
Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
Corrective Assignment to Correct the Remove Application 12092129 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
Patent Release
Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Change of Name
Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
Merger
Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
Corrective Assignment to Correct the Nature of Conveyance Listed Change of Name Should Be Merger and Change Previously Recorded at Reel: 040652 Frame: 0180. Assignor(S) Hereby Confirms the Merger and Change of Name.
Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
Corrective Assignment to Correct the Remove Patents 8108266 and 8062324 and Replace Them with 6108266 and 8060324 Previously Recorded on Reel 037518 Frame 0292. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
Assignment of Assignor's Interest
Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 039361 Frame 0212. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
Corrective Assignment to Correct the Remove Application 12681366 Previously Recorded on Reel 038017 Frame 0058. Assignor(S) Hereby Confirms the Security Agreement Supplement.
May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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Assignment of Assignor's Interest
Aug 25, 2017
From: SIMPSON, CINDY REIDSEMA; HERRICK, MATTHEW T.; ETHERINGTON, GREGORY S.; LEGG, JAMES DEREK
To: MOTOROLA, INC.
Reel/Frame 043400/0795 →