Granted Patent B2

US 7,339,275 · App. 10/995,818 · Granted Mar 4, 2008

Abstract

Claims (23)

1. A method for fabricating a semiconductor device assembly, the method comprising:

providing a first integrated circuit chip having a first surface, a plurality of conductive contacts disposed at said first surface, and a plurality of integrated circuits, each of said plurality of integrated circuits electrically coupled to at least one of said plurality of conductive contacts,

depositing an organic cushioning layer over said first integrated circuit chip;

patterning said organic cushioning layer to form a plurality of openings to expose at least the conductive contacts;

depositing a robust metal layer overlying said integrated circuits and filling said plurality of openings;

patterning said robust metal layer to form a plurality of robust metal portions, at least some of which serve as landing pads, wherein the robust metal portions spatially redistribute at least one of said plurality of conductive contacts, wherein each robust metal portion comprises a single contiguous metal or alloy, and directly contacts at least one of the plurality of conductive contacts and can withstand high current operation therethrough, and wherein at least one of said plurality of robust metal portions at least partially overlies the organic cushioning layer such that the robust metal portion can withstand impact stresses;

disposing a first portion of a second integrated circuit chip overlying at least a first portion of said first integrated circuit chip so that a second portion of said second integrated circuit chip extends beyond said first integrated circuit chip, wherein said second integrated circuit chip has a second surface and comprises a plurality of first bonding members disposed at said second surface and said second surface is disposed adjacent said first surface of said first integrated circuit chip;

disposing a first portion of a third integrated circuit chip overlying at least a second portion of said first integrated circuit chip so that a second portion of said third integrated circuit chip extends beyond said first integrated circuit chip, wherein said third integrated circuit chip has a third surface and comprises a plurality of second bonding members disposed at said third surface and said third surface is disposed adjacent said first surface of said first integrated circuit chip;

bonding each one of a first set of said plurality of bonding members to one of said plurality of robust metal portions; and

bonding each of a first set of said plurality of second bonding member to one of said plurality of robust metal portions;

depositing an underfill material on said first surface of said first integrated circuit chip; and

curing said underfill material.

2. The method for fabricating a semiconductor device assembly of claim 1 , wherein said first set of said plurality of first bonding members is disposed at said first portion of said second integrated circuit chip.

3. The method for fabricating a semiconductor device assembly of claim 1 , wherein a second set of said plurality of bonding members is disposed at said second portion of said second integrated circuit chip.

4. The method for fabricating a semiconductor device assembly of claim 1 , wherein each of said plurality of first bonding members comprises a solder material and the step of bonding each one of a first set of said plurality of first bonding members to one of said plurality of conductive pads comprises reflowing each one of said first set of said plurality of first bonding members.

5. The method for fabricating a semiconductor device assembly of claim 1 , wherein said underfill material comprises a no-flow underfill material and the step of depositing an underfill material is performed before the step of bonding.

6. The method for fabricating a semiconductor device assembly of claim 5 , wherein the steps of bonding and curing are performed substantially simultaneously.

7. The method for fabricating a semiconductor device assembly of claim 1 , wherein said first integrated circuit chip comprises a plurality of contacts adapted to be used as probe sites, and wherein said method further comprises the step of placing probe tips on the plurality of contacts to electrically test said first integrated circuit chip.

8. The method for fabricating a semiconductor device assembly of claim 7 , wherein said second integrated circuit chip further comprises a plurality of integrated circuits, wherein each one of said plurality of integrated circuits of said second integrated circuit chip is in electrical communication with a corresponding bonding member, and wherein the method further comprises the step of placing probe tips on the plurality of contacts to electrically test said second integrated circuit chip.

9. The method of claim 1 , wherein forming the robust metal portion comprises forming a power metal layer.

10. The method of claim 9 , wherein forming the robust metal portion comprises forming a power copper layer.

11. The method of claim 10 , wherein forming the robust metal portion comprises forming a power copper layer having a thickness greater than 4 microns.

12. The method of claim 10 , wherein forming the robust metal portion includes forming a robust metal portion configured high current operation of least about 15 Amps.

Assignments (22)