Patent Assignment
Reel/Frame 041717/0736
Assignment of Assignor's Interest
Recorded: 2017-02-15
Pages: 10
Assignor
NORTH STAR INNOVATIONS INC.
Executed: 2016-10-06
Assignee
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
NO.8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK,, HSINCHU, TAIWAN
Covered Properties
(125)
Lithographic Template Having a Repaired Gap Defect Method of Repair and Use
Reconfigurable Vector-Fft/Ifft, Vector-Multiplier/Divider
Digital and Rf System and Method Therefor
Low Stress Semiconductor Die Attach
Non-Resolving Mask Tiling Method for Flare Reduction
Plated Metal Transistor Gate and Method of Formation
Patent:
6,686,282 →
Application:
10/403,967 →
Method to Passivate Conductive Surfaces During Semiconductor Processing
Bit Exactness Support in Dual-Mac Architecture
Method and Apparatus for Reduced Power Consumption Adc Conversion
Activation Plate for Electroless and Immersion Plating of Integrated Circuits
Bonding Pad for a Packaged Integrated Circuit
Method for Converting a Planar Transistor Design to a Vertical Double Gate Transistor Design
Method of forming a transistor having multiple channels
Wirebonded Assemblage Method and Apparatus
Semiconductor Device with Nanoclusters
Low Threshold Voltage Circuit Employing a High Threshold Voltage Output Stage
Transistor Having Three Electrically Isolated Electrodes and Method of Formation
Warpage Control of Array Packaging
Method for Forming a Semiconductor Device with Local Semiconductor-on-Insulator (Soi)
Die Encapsulation Using a Porous Carrier
Land Grid Array Packaged Device and Method of Forming Same
Schottky Device
Method of Forming a Nanocluster Charge Storage Device
Ultra-Thin Die and Method of Fabricating Same
Method and System for Performing Deblocking Filtering
High K Dielectric Film
Dynamic Latch Having Integral Logic Function and Method Therefor
Semiconductor Device Having Conductive Spacers in Sidewall Regions and Method for Forming
Method for Forming a Layer Using a Purging Gas in a Semiconductor Process
Patent:
7,015,153 →
Application:
10/969,634 →
Method of Integrating Optical Devices and Electronic Devices on an Integrated Circuit
Multi-Chips Semiconductor Device Assemblies and Methods for Fabricating the Same
Flexible Carrier and Release Method for High Volume Electronic Package Fabrication
Layout Modification Using Multilayer-Based Constraints
Asymmetric Spacers and Asymmetric Source/Drain Extension Layers
Three-Dimensional Package
Process of Forming a Non-Volatile Memory Cell Including a Capacitor Structure
Transistor Having Multiple Channels
Enhancement Mode Transceiver and Switched Gain Amplifier Integrated Circuit
Dual Metal Gate Electrode Semiconductor Fabrication Process and Structure Thereof
Patent:
7,074,664 →
Application:
11/092,418 →
Conducting Metal Oxide with Additive as P-Mos Device Electrode
Semiconductor Die Edge Reconditioning
Method of Making Planar Double Gate Silicon-on-Insulator Structures
Method of Fabricating a Substrate for a Planar, Double-Gated, Transistor Process
Mechanical Integrity Evaluation of Low-K Devices with Bump Shear
Method of Fabricating a Nonvolatile Storage Array with Continuous Control Gate Employing Hot Carrier Injection Programming
Method of Forming a Finfet Structure
Packaged Device and Method of Forming Same
Method of Forming Double Gate Transistors Having Varying Gate Dielectric Thicknesses
Multi-Channel Transistor Structure and Method of Making Thereof
Finfet Structure with Contacts
Microelectronic Assembly and Method for Forming the Same
Nicam Processing Method
Region Clustering Based Error Concealment for Video Data
Semiconductor Device with Reduced Package Cross-Talk and Loss
Method for Forming a Planar and Vertical Semiconductor Structure Having a Strained Semicondutor Layer
Electronic Device and a Process for Forming the Electronic Device
Method of Forming a Semiconductor Device with Decreased Undercutting of Semiconductor Material
Split Gate Memory Cell in a Finfet
High Linearity and Low Noise Amplifier with Continuously Variable Gain Control
Process for Forming an Electronic Device Including Semiconductor Fins
Replacement Pointer Control for Set Associative Cache and Method
Integrated Circuit Having Pads and Input/Output (I/O) Cells
Method of Making a Multi-Gate Device
Process of Forming an Electronic Device Including a Semiconductor Layer and Another Layer Adjacent to an Opening Within the Semiconductor Layer
A Method of Making Metal Gate Transistors
Twisted Dual-Substrate Orientation (Dso) Substrates
Data Processor and Methods Thereof
Method of Making Stacked Die Package
Dyadic Spatial Re-Sampling Filters for Inter-Layer Texture Predictions in Scalable Image Processing
Heat Spreader for Semiconductor Package
Methods and Apparatus for a Quad Flat No-Lead (Qfn) Package
Digital Bandgap Reference and Method for Producing Reference Signal
Method for Estimating Processor Energy Usage
Method of Packaging Semiconductor Devices
Method and System for Sampling Video Data
Packaged Device and Method of Forming Same
Method to Passivate Conductive Surfaces During Semiconductor Processing
Electronic Device with Connection Bumps
Flip Chip and Wire Bond Semiconductor Package
Methods and Apparatus for Emi Shielding in Multi-Chip Modules
Output Correction Circuit for Three-Axis Accelerometer
Apparatus and Method for Decoding Bursts of Coded Information
Method of Packaging an Integrated Circuit Die
Data Acquisition Messaging Using Special Purpose Registers
Adjustable Dac and Applications Thereof
Method of Fabricating a Mos Device with Non-SIO2 Gate Dielectric
Multi-Channel Transistor Structure and Method of Making Thereof
Read Reference Technique with Current Degradation Protection
Method and System for Filtering Image Data
Method of Fabricating a Substrate for a Planar, Double-Gated, Transistor Process
Method of Forming a Finfet and Structure
System and Method for Parallel Video Processing in Multicore Devices
System and Method for Using a Task Starvation Indication to Prevent Starvations of Tasks in a Multiple Processing Entity System
System and Method for Load Balancing a Video Signal in a Multi-Core Processor
Device and Method for Finding Extreme Values in a Data Block
Electronic Device Including a Gated Diode
Semiconductor Device with a Buffer Region with Tightly-Packed Filler Particles
Methods for Forming Quad Flat No-Lead (Qfn) Packages
Ultra-Thin Die and Method of Fabricating Same
Flexible Carrier for High Volume Electronic Package Fabrication
Quad Flat No-Lead (Qfn) Packages
Substrate Bonding with Metal Germanium Silicon Material
Video Scene Change Detection and Encoding Complexity Reduction in a Video Encoder System Having Multiple Processing Devices
Cmos Integration with Metal Gate and Doped High-K Oxides
Real Time Clock Monitoring Method and System
Stacked Device Assembly with Integrated Coil and Method of Forming Same
Video Decoder Plus a Discrete Cosine Transform Unit
Video Decoding with Error Detection and Concealment
Data Processor Coupled to a Sequencer Circuit That Provides Efficient Scalable Queuing and Method
Multiple-Stage, Signal Edge Alignment Apparatus and Methods
Semiconductor Device with Oxygen-Diffusion Barrier Layer and Method for Fabricating Same
Microcontroller Unit and Method Therefor
Shielded Multi-Layer Package Structures
Die Assemblies
Method, Integrated Circuit, and Communication Unit for Scheduling a Processing of Packet Stream Channels
Gain Enhanced Switched Capacitor Circuit and Method of Operation
Patent:
8,026,760 →
Application:
12/846,475 →
Switched-Capacitor Amplifier Circuit
Patent:
8,198,937 →
Application:
13/048,113 →
System and Method for Efficient Image Feature Extraction
Back Side Alignment Structure and Manufacturing Method for Three-Dimensional Semiconductor Device Packages
Substrate Bonding with Metal Germanium Silicon Material
Transistors and Semiconductor Devices with Oxygen-Diffusion Barrier Layers
Circuit for Generating Multi-Phase Non-Overlapping Clock Signals
Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit
Patent:
8,510,695 →
Application:
13/484,328 →
Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit
Techniques for Electromigration Stress Mitigation in Interconnects of an Integrated Circuit Design
Related Assignments
(24)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement
Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
Security Agreement
Nov 12, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031626/0218 →
Change of Name
Nov 23, 2015
From: SIGMATEL INC.
To: SIGMATEL, LLC
Reel/Frame 037152/0127 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0793 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
Assignment and Assumption of Security Interest in Patents
Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
Assignment and Assumption of Security Interest in Patents
Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
Assignment of Assignor's Interest
Jan 25, 2016
From: SIGMATEL, LLC
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037583/0428 →
Assignment of Assignor's Interest
Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
Corrective Assignment to Correct the Assignee Name Previously Recorded at Reel: 037354 Frame: 0773. Assignor(S) Hereby Confirms the Patent Release.
Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
Release of Security Interest
Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
Release of Security Interest
Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
Corrective Assignment to Correct the Remove Patents 8108266 and 8062324 and Replace Them with 6108266 and 8060324 Previously Recorded on Reel 037518 Frame 0292. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
Corrective Assignment to Correct the to Correct the Application No. from 13,883,290 to 13,833,290 Previously Recorded on Reel 041703 Frame 0536. Assignor(S) Hereby Confirms the the Assignment and Assumption of Security Interest in Patents..
Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
323.01(C) Assignment or Change of Name Improperly Filed and Recorded by Another Person Against Owner's Patent
Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 037486 Frame 0517. Assignor(S) Hereby Confirms the Assignment and Assumption of Security Interest in Patents.
Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040928 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
Corrective Assignment to Correct the Remove Application 11759915 and Replace It with Application 11759935 Previously Recorded on Reel 040925 Frame 0001. Assignor(S) Hereby Confirms the Release of Security Interest.
Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →