IP Library Granted Patent US 7,489,026
Granted Patent B2
US 7,489,026 · App. 11/590,327 · Granted Feb 10, 2009

Methods and apparatus for a Quad Flat No-Lead (QFN) package

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Quick Facts
Patent No.
US 7,489,026
App. No.
11/590,327
Granted
Feb 10, 2009
Kind
B2
Abstract

Methods and apparatus are provided for decreasing the size of Quad Flat No-Lead (QFN) packages ( 300, 400 ) down to chip-scale packages. Such QFN packages include a first semiconductor chip ( 310, 410 ), a plurality of recessed leads ( 306, 406, 408, 411 ) having mold lock features, and a mold material 340, 440 substantially encasing all sides of the semiconductor chip. An active surface ( 314, 414 ) of the semiconductor chip is oriented toward a mounting side ( 307, 407 ) of the QFN package, and a plurality of wire bonds 330, 430 disposed between the active surface and the mounting side couple the active side to the leads. The QFN packages may also include a second semiconductor chip ( 452 ) coupled to a plurality of leads ( 408 ) and to the first semiconductor chip via wire bonds ( 431, 432 ) in a manner similar to the first semiconductor chip.

Claims (44)

1. A Quad Flat No-Lead (QFN) package, the QFN package comprising:

a mold material defining the QFN package including a mounting side having a perimeter;

a semiconductor chip including an active surface and an inactive surface housed within the mold material;

a plurality of leads exposed on the mounting side and partially housed within the mold material, the plurality of leads included within the perimeter of the mold material; and

a plurality of wire bonds configured to couple the plurality of leads to the semiconductor chip, wherein the active surface is oriented toward the mounting side and the plurality of wire bonds are disposed between the active surface and the mounting side within the mold material.

2. The QFN package of claim 1 , wherein the plurality of leads comprises at least one mold lock coupling each of the plurality of leads to the mold material.

3. The QFN package of claim 1 , wherein each of the plurality of leads comprises a jogged-shape to couple each of the plurality of leads to the mold material.

4. The QFN package of claim 1 , further comprising a top side located substantially opposite the mounting side and a plurality of lateral sides, wherein:

a first center of the semiconductor chip is oriented substantially in a second center of the QFN package, and

the second center is located at a center of the mounting side, the top side, and the plurality of sides.

5. The QFN package of claim 1 , wherein a width of the mounting side is not greater than about 2.5 mm.

6. The QFN package of claim 5 , wherein a height of the QFN package is not greater than about 1 mm.

7. The QFN package of claim 1 , wherein a ratio of a width of the QFN package to a width of the semiconductor chip is no greater than 1.2.

8. The QFN package of claim 1 , wherein at least one of the plurality of leads includes a jogged shape having a two-tiered surface oriented toward the mounting side, and wherein at least one wire bond is coupled to the active side and the two-tiered surface.

9. A QFN package having a mounting side, the QFN package comprising:

a first semiconductor chip including a first active surface and a first inactive surface;

a second semiconductor chip including a second active surface and a second inactive surface;

a first plurality of leads oriented on the mounting side; and

a first plurality of wire bonds coupling the first plurality of leads to the first semiconductor chip, wherein:

the first active surface is oriented toward the mounting side, and

the first plurality of wire bonds are disposed between the first active surface and the mounting side.

10. The QFN package of claim 9 , further comprising:

a second plurality of leads oriented on the mounting side; and

a second plurality of wire bonds coupling the second plurality of leads to the second semiconductor chip, wherein the second plurality of wire bonds are disposed between the second active surface and the mounting side.

11. The QFN package of claim 10 , further comprising:

a first wire bond coupling a first lead to the first active side, wherein the first wire bond is disposed between the first active surface and the mounting side.

12. The QFN package of claim 11 , further comprising:

a second wire bond coupling the first lead to the second active side, wherein the second wire bond is disposed between the second active surface and the mounting side.

13. The QFN package of claim 10 , wherein the first plurality of leads and second plurality of leads each comprise at least one mold lock coupling each of the first plurality of leads and the second plurality of leads to the mold material.

14. The QFN package of claim 10 , wherein each of the first plurality of leads and the second plurality of leads comprise a jogged-shape to couple each of the first plurality of leads and the second plurality of leads to the mold material.

15. The QFN package of claim 9 , wherein a width of the mounting side is not greater than about 5.5 mm.

16. The QFN package of claim 9 , wherein the QFN package includes a height not greater than about 1 mm.

17. The QFN package of claim 15 , wherein the width of the mounting side is 5 mm.

18. The QFN package of claim 17 , wherein the QFN package includes a height of about 0.8 mm.

19. The QFN package of claim 9 , wherein the first plurality of leads each include a height in the range of about 0.15 mm to about 0.4 mm.

20. The QFN package of claim 1 , wherein the plurality of leads each include a height in the range of about 0.15 mm to about 0.4 mm.

21. A QFN package having a mounting side, the QFN package comprising:

a first semiconductor chip including a first active surface oriented toward the mounting side;

a second semiconductor chip including a second active surface oriented toward the mounting side;

a lead oriented on the mounting side;

a first wire bond coupling the lead to the first active surface; and

a second wire bond coupling the lead to the second active surface.

22. The QFN package of claim 21 , wherein the first wire bond is disposed between the first active surface and the mounting side, and the second wire bond is disposed between the second active surface and the mounting side.

23. The QFN package of claim 21 , wherein a width of the mounting side is not greater than about 5.5 mm.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
323.01(C) ASSIGNMENT OR CHANGE OF NAME IMPROPERLY FILED AND RECORDED BY ANOTHER PERSON AGAINST OWNER'S PATENT Recorded Oct 3, 2019
From: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 052459/0656 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2017
From: NORTH STAR INNOVATIONS INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 041717/0736 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0793 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded May 19, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 022703/0405 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2006
From: WANG, JAMES J.; MCDONALD, WILLIAM G.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018489/0773 →