Semiconductor die edge reconditioning
View Patent ↗An integrated circuit has a semiconductor substrate and an interconnect layer that mechanically relatively weak and susceptible to cracks and delamination. In the formation of the integrated circuit from a semiconductor wafer, a cut is made through the interconnect layer to form an edge of the interconnect layer. This cut may continue completely through the wafer thickness or stop short of doing so. In either case, after cutting through the interconnect layer, a reconditioning layer is formed on the edge of the interconnect layer. This reconditioning layer seals the existing cracks and delaminations and inhibits the further delamination or cracking of the interconnect layer. The sealing layer may be formed, for example, before the cut through the wafer, after the cut through the wafer but before any packaging, or after performing wirebonding between the interconnect layer and an integrated circuit package.
1. A method of making an integrated circuit, comprising:
providing a semiconductor wafer having a major surface;
forming active circuitry on the major surface of the semiconductor wafer;
forming a dielectric layer over the active circuitry;
forming an interconnect layer over the dielectric layer;
forming a plurality of bond sites over the interconnect layer;
performing a cutting operation to form a plurality of grooves through the interconnect layer, the dielctric layer and partially through the semiconductor wafer;
applying a sealing material to coat the inside of each of the plurality of grooves, wherein the sealing material is not applied over a substatial portion of the major surface of the semiconductor wafer; and
performing a separating operation to separate the semiconductor wafer into a plurality of singulated integrated circuit die, wherein the separtaing operation begfins in the plurality of grooves after the sealing material is applied, and wherein the sealing material remains on a side of the groove after the separating operation.
2. The method of claim 1 , wherein the step of applying the sealing material further comprises applying the sealing material around the bond site.
3. The method of claim 1 , further comprising:
placing an integrated circuit die of the plurality of singulated integrated circuit die in a cavity of an integrated circuit package substrate; and
wirebonding from a bond site of the plurality of bond sites to the integrated circuit package.
4. The method of claim 1 , wherein performing a cutting operation further comprises performing a sawing operation to form the plurality of grooves.
5. The method of claim 1 , wherein performing a separating operation further comprises performing a sawing operation beginning in the plurality of grooves.
6. The method of claim 1 , wherein applying a sealing material further comprises applying a sealing materail comprising one of an epoxy, a polymer, a glass, or a ceramic.
7. A method of forming an integrated circuit, comprising:
providing a semiconductor wafer;
forming active circuitry on the semiconductor wafer;
forming a dielectric layer over the active circuitry;
forming an interconnect layer over the dielectric layer;
forming a plurality of bond sites over the interconnect layer;
cutting through the interconnect layer, the dielctric layer, and partially through the semiconductor wafer to form a groove;
coating the groove with a sealing material;
cutting completely through the semiconductor wafer beginning in the groove to form a plurality of semiconductor die from the semiconductor wafer, wherein cutting completely through the semiconductor wafer occurs after the groove is coated with the sealing material, and wherein the sealing material remains on a side of the groove after cutting completely through the semiconductor wafer; and
placing a semiconductor die of the plurality of semiconductor die in a cavity of a package substrate.
8. The method of claim 7 , wherein cutting completely through the semiconductor wafer further comprises using a separate each die from the wafer, wherein the separator is placed in the groove and functions to mechanically separate the plurality of semiconductor die from each other.
9. The method of claim 7 , wherein the groove with a sealing material further comprises coating the groove with a sealing material comprising one of an epoxy, a polymer, a glass, or a ceramic.
10. The method of claim 7 , wherein coating the groove with a sealing material further comprises coating the groove with a sealing material that applies a compressive stress to the semiconductor die.