Apparatus and method for decoding bursts of coded information
View Patent ↗A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.
1. A decoding circuit, comprising:
a mixed modulation memory access circuit, responsive to burst rejection information, that is operative to selectively access burst memory locations containing a valid burst of coded bits and to avoid accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information.
2. The decoding circuit of claim 1 wherein the mixed modulation memory access circuit accesses a valid burst when the burst rejection information indicates that the memory location contains valid bursts and the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.
3. The decoding circuit of claim 2 further comprising:
a depuncturer that is operative to generate depunctured information based on at least one of the valid burst and the zero confidence information; and
a decoder that is operative to generate decoded information based on the depunctured information.
4. The decoding circuit of claim 1 further comprising a burst rejection register, operatively coupled to the mixed modulation memory access circuit, that is operative store the burst rejection information.
5. The decoding circuit of claim 1 further comprising memory, operatively coupled to the mixed modulation memory access circuit, that is operative to store a contiguous block of coded bits, wherein the contiguous block of coded bits includes at least one of the valid burst of coded bits and the rejected burst of coded bits.
6. The decoding circuit of claim 5 wherein the burst rejection information indicates whether a burst of coded bits stored in the contiguous block is one of valid and rejected.
7. The decoding circuit of claim 6 wherein the burst of coded bits is valid when a majority of coded bits stored in the contiguous block have a same modulation type as the burst of coded bits.
8. The decoding circuit of claim 1 wherein the mixed modulation memory access circuit comprises:
a mapping module that is operative to assign each coded bit of a stream of coded bits a burst identifier and a bit identifier;
a burst rejection module, operatively coupled to the mapping module, that is operative to determine whether a burst of coded bits is one of valid and rejected based on the burst rejection information and the burst identifier;
an address offset module that is operative to determine a memory address offset based on the burst identifier and the burst rejection information; and
an address generator, operatively coupled to the address offset module, that is operative to determine a memory read address based on the memory address offset and the bit identifier, wherein the mixed modulation memory circuit accesses the burst memory locations containing the valid burst based on the memory read address.
9. A mixed modulation decoding circuit, comprising:
a processor that includes a burst rejection generator that is operative to generate burst rejection information based on a modulation type for each burst of coded bits of a logical channel; and
a decoding circuit that is operative to generate decoded information by selectively accessing burst memory locations containing a valid burst of coded bits and by avoiding accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information.
10. The mixed modulation decoding circuit of claim 9 wherein the decoding circuit comprises:
a mixed modulation memory access circuit that accesses memory locations when the burst rejection information indicates that the memory location contains the valid burst and that generates zero confidence information when the burst rejection information indicates that that the memory location contains the rejected burst; and
a burst rejection register, operatively coupled to the mixed modulation memory access circuit, that is operative to store the burst rejection information.
11. The mixed modulation decoding circuit of claim 10 wherein the decoding circuit further comprises:
memory, operatively coupled to the mixed modulation memory access circuit, that is operative to store a contiguous block of coded bits, wherein the contiguous block includes at least one of the valid burst of coded bits and the rejected burst of coded bits;
a depuncturer that is operative to generate depunctured information based on at least one of the valid burst of coded bits and the zero confidence information; and
a decoder, operatively coupled to the depuncturer, that is operative to generate the decoded information based on the depunctured information.
12. The mixed modulation decoding circuit of claim 9 wherein the burst rejection information indicates whether each burst is one of valid and rejected.
13. The mixed modulation decoding circuit of claim 12 wherein the burst rejection generator determines whether a burst is one of valid and rejected based on a majority vote of the modulation type for each burst of coded bits.
14. The mixed modulation decoding circuit of claim 9 wherein the decoded information is processed by the processor to generate output information for a user interface.
15. A decoding method, comprising:
selectively accessing burst memory locations containing a valid burst of coded bits and avoiding accessing burst memory locations containing a rejected burst of coded bits based on burst rejection information.
16. The method of claim 15 further comprising:
reading the burst memory locations containing the valid burst when the burst rejection information indicates that the memory location contains valid bursts; and
generating zero confidence information when the burst rejection information indicates that the memory locations contain rejected bursts.
17. The method of claim 16 further comprising:
generating depunctured information based on at least one of the valid burst and the zero confidence information; and
generating decoded information based on the depunctured information.
18. The method of claim 15 further comprising storing the burst rejection information in a burst rejection register.
19. The method of claim 15 further comprising storing a contiguous block of coded bits in memory, wherein the contiguous block of coded bits includes at least one of the valid burst of coded bits and the rejected burst of coded bits.
20. The method of claim 19 wherein the burst rejection information indicates whether a burst of coded bits stored in the contiguous block is one of valid and rejected.
21. The method of claim 20 wherein the burst of coded bits is valid when a majority of coded bits stored in the contiguous block have a same modulation type as the burst of coded bits.
22. The method of claim 15 comprising:
receiving bursts of coded bits via a wireless channel; and
storing the received bursts of coded bits in memory.