Method of forming a nanocluster charge storage device
View Patent ↗A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
1. A method of forming a nanocluster charge storage device, comprising:
providing a substrate having a first dopant well associated with the nanocluster charge storage device and a second dopant well associated with a semiconductor device not having nanoclusters;
forming a first gate stack overlying the first dopant well and having a first conductive gate material layer that forms a gate electrode in the first gate stack, the first conductive gate material layer overlying a plurality of nanoclusters embedded in a first gate dielectric layer, the first conductive gate material layer underlying a portion of a second conductive gate material layer; and
forming a second gate stack overlying the second dopant well using a portion of the second conductive gate material layer overlying the second dopant well as a gate electrode in the second gate stack, a portion of the second conductive gate material layer that overlies the first conductive gate material layer is removed.
2. The method of claim 1 further comprising:
removing the portion of the second conductive gate material layer that overlies the first conductive gate material layer by masking all areas away from the first dopant well and selectively etching the second conductive gate material layer.
3. The method of claim 1 further comprising:
forming the first conductive gate material layer and the second conductive gate material layer using doped polysilicon, a metal or a metal alloy.
4. The method of claim 3 further comprising:
implementing the first conductive gate material layer with a material that is different from the second conductive gate material layer.
5. The method of claim 1 further comprising:
forming the first gate dielectric layer comprising forming a gate oxide layer and a second gate oxide layer overlying and surrounding the nanocluster layer, wherein the first gate dielectric and the first conductive gate material layer are formed overlying both the first dopant well and the second dopant well; and
selectively etching from areas overlying the second dopant well the first conductive gate material layer, the first gate dielectric layer and the nanocluster layer using a combination of a wet etch and a dry etch.
6. The method of claim 1 further comprising:
forming the second gate stack by forming a second gate dielectric layer and the second conductive gate material layer overlying a portion of the second dopant well, the second conductive gate material layer overlying the second gate dielectric layer.
7. The method of claim 6 further comprising:
forming the second gate dielectric layer’ of silicon dioxide or silicon oxynitride.
8. The method of claim 1 further comprising:
forming a nitride layer in the first gate stack and overlying the first conductive gate material and between a portion of the first conductive gate material and the second conductive gate material;
forming an oxide layer overlying and in physical contact with the nitride layer, the nitride layer and oxide layer functioning as an etch stop layer when removing the second conductive gate material and the nitride layer also functioning as an antireflective coating when forming the gate electrode in the first gate stack.
9. The method of claim 1 further comprising:
forming the first gate dielectric layer of an oxide or an oxynitride of a compound containing at least one of hafnium, lanthanum, aluminum and silicon.
10. The method of claim 1 further comprising:
forming the plurality of nanoclusters embedded in the first gate dielectric layer overlying the first dopant well and the second dopant well by forming a layer of doped or undoped semiconductor nanocrystals, metal nanocrystals, nanocrystals of two or more doped or undoped semiconductors, or metal alloy nanocrystals.
11. The method of claim 1 further comprising:
forming a first source and a first drain around the first gate stack and within the first dopant well to form the charge storage device as a nonvolatile memory (NVM) transistor; and
forming a second source and a second drain around the second gate stack and within the second dopant well to form a periphery transistor.
12. The method of claim 1 further comprising:
forming a semiconductor device from the second gate stack, the semiconductor device enabling charging and discharging of the nanocluster charge storage device.
13. A method comprising:
providing a substrate;
forming a first dopant well and a second dopant well in the substrate;
forming a layer of nanoclusters embedded in a first gate dielectric overlying the first dopant well and the second dopant well;
forming a first conductive gate material layer overlying the layer of nanoclusters;
forming a nitride layer overlying the first conductive gate material layer;
forming a storage stack overlying the first dopant well by patterning and removing the nitride layer, the first conductive gate material layer and the layer of nanoclusters from areas other than overlying the first dopant well;
forming a second gate dielectric overlying the second dopant well, the second gate dielectric having no nanoclusters;
forming a second conductive gate material layer overlying the second gate dielectric and the storage stack;
forming an anti-reflective coating layer overlying the second conductive gate material layer;
patterning the second conductive gate material layer to form a first gate stack having the second conductive gate material layer as a gate electrode thereof while removing the second conductive gate material layer from the storage stack; and
forming a second gate stack overlying the first dopant well by removing a portion of the storage stack, the second gate stack using the first conductive gate material layer as a gate electrode of a charge storage device having nanoclusters.
14. The method of claim 13 further comprising:
forming a first source and a first drain around the first gate stack and within the second dopant well to form a transistor; and
forming a second source and a second drain around the second gate stack and within the first dopant well to complete formation of the charge storage device.
15. The method of claim 13 further comprising:
forming the first conductive gate material layer of doped polysilicon, metal or a metal alloy.
16. The method of claim 13 further comprising:
forming the second conductive gate material layer ( 44 ) of doped polysilicon, metal or a metal alloy.
17. The method of claim 13 further comprising:
forming the layer of nanoclusters embedded in the first gate dielectric overlying the first dopant well and the second dopant well by forming a layer of doped or undoped semiconductor nanocrystals, metal nanocrystals, nanocrystals of two or more doped or undoped semiconductors, or metal alloy nanocrystals.
18. The method of claim 12 further comprising:
forming the first gate dielectric of an oxide or an oxynitride of a compound containing at least one of hafnium, lanthanum, aluminum and silicon.
19. The method of claim 13 further comprising:
forming the second gate dielectric of silicon dioxide or silicon oxynitride.
20. A method of forming a nanocluster charge storage device, comprising:
providing a substrate having a memory dopant well associated with the nanocluster charge storage device and a periphery dopant well associated with a semiconductor device not having nanoclusters;
forming a layer of nanoclusters embedded in a first gate dielectric overlying the memory dopant well;
forming a first gate material layer overlying the layer of nanoclusters;
patterning the layer of nanoclusters and the first gate material layer to exist only overlying the memory dopant well;
forming a second gate material layer overlying the periphery dopant well and also overlying the layer of nanoclusters and the first gate material layer after formation of the first gate material layer;
forming a periphery device gate stack by removing the second gate material layer from areas other than a predetermined periphery area overlying the periphery dopant well; and
subsequently forming a nanocluster charge storage device gate stack by patterning the layer of nanoclusters and the first gate material layer overlying the memory dopant well, wherein the charge storage device gate stack is formed after formation of the periphery device gate stack even though the first gate material layer is formed prior to the second gate material layer.
21. The method of claim 20 further comprising:
forming an etch stop layer directly overlying the first gate material layer for endpoint detection during removal of the second gate material layer overlying the first gate material layer.
22. A method of forming a nanocluster charge storage device, comprising:
providing a substrate having a memory dopant well associated with the nanocluster charge storage device and a periphery dopant well associated with a semiconductor device not having nanoclusters;
forming a layer of nanoclusters embedded in a first gate dielectric overlying the memory dopant well;
forming a first gate material layer overlying the layer of nanoclusters;
patterning the layer of nanoclusters and the first gate material layer to exist only overlying the memory dopant well;
forming a second gate material layer overlying the periphery dopant well and also overlying the layer of nanoclusters and the first gate material layer after formation of the first gate material layer;
removing the second gate material layer from areas other than a predetermined periphery area overlying the periphery dopant well; and
using a mask to selectively form at a substantially same time a periphery device gate stack and a nanocluster charge storage gate.