IP Library Granted Patent US 8,634,466
Granted Patent B2
US 8,634,466 · App. 12/405,305 · Granted Jan 21, 2014

Video decoder plus a discrete cosine transform unit

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Quick Facts
Patent No.
US 8,634,466
App. No.
12/405,305
Granted
Jan 21, 2014
Kind
B2
Abstract

A video encoder and a decoder analyze the spatial content video data in an H.264 stream using the discrete cosine transform (DCT). Although the DCT is computed as part of the H.264 encoding process, it is not computed as part of the decoding process. Thus, one would compute the DCT of the video data after it has been reconstructed by the video decoder for video post-processing or enhanced video encoding. A method for accelerating the computation of the DCT at the decoder side when transmitting intra-mode macroblocks uses information computed by the encoder and transmitted as part of the H.264 video stream.

Claims (45)

1. An apparatus comprising:

a decoder that receives

a prediction mode flag and

a discrete cosine transform (DCT) of a residual macroblock

and provides a prediction macroblock;

control circuitry which receives the prediction mode flag, wherein the prediction mode flag indicates which one of a plurality of intra prediction modes has been selected,

said control circuitry providing one or more control signals;

computation circuitry coupled to the control circuitry to receive the one or more control signals, said computation circuitry also receiving the prediction macroblock,

when a first one of the plurality of intra prediction modes has been selected said computation circuitry performing a first plurality of computations on the prediction macroblock to produce a DCT of the prediction macroblock,

when a second one of the plurality of intra prediction modes has been selected said computation circuitry performing a second plurality of computations on the prediction macroblock to produce the DCT of the prediction macroblock,

wherein the first plurality of computations and the second plurality of computations are different; and

addition circuitry coupled to the computation circuitry to receive the DCT of the prediction macroblock, the addition circuitry adding the DCT of the prediction macroblock to the DCT of a residual macroblock to produce a DCT of the macroblock.

2. An apparatus as in claim 1 , wherein the first plurality of computations comprises a first number of additive operations and a second number of scaling operations, and wherein the second plurality of computations comprises a third number of additive operations and a fourth number of scaling operations.

3. An apparatus as in claim 2 , wherein when the first one of the plurality of intra prediction modes is a DC mode, the first number of additive operations is zero and the second number of scaling operations is not greater than one.

4. An apparatus as in claim 3 , wherein when the second one of the plurality of intra prediction modes is a vertical mode, the third number of additive operations is not greater than eight and the fourth number of scaling operations is not greater than six.

5. An apparatus as in claim 3 , wherein when the second one of the plurality of intra prediction modes is a horizontal mode, the third number of additive operations is not greater than eight and the fourth number of scaling operations is not greater than six.

6. An apparatus as in claim 3 , wherein when the second one of the plurality of intra prediction modes is a diagonal down left mode, the third number of additive operations is not greater than thirty-three and the fourth number of scaling operations is not greater than eleven.

7. An apparatus as in claim 1 , wherein data provided in the macroblock is determined by the H.264 standard.

8. An apparatus as in claim 1 , further comprising:

circuitry for generating a video output, said circuitry for generating the video output being coupled to the addition circuitry for receiving the DCT of the macroblock,

said circuitry for generating the video output combining a reconstructed macroblock and the DCT of the macroblock to generate the video output.

9. An apparatus as in claim 8 , wherein the video output is a compressed video stream.

10. An apparatus as in claim 8 , wherein the circuitry for generating the video output comprises decoding circuitry.

11. An apparatus as in claim 8 , wherein the circuitry for generating the video output comprises encoding circuitry.

12. A method for generating a discrete cosine transform (DCT) of a macroblock, the method comprising:

providing a prediction mode flag, wherein the prediction mode flag indicates which one of a plurality of intra prediction modes has been selected;

providing a DCT of a residual macroblock;

providing a prediction macroblock responsive to the prediction mode flag and the DCT of the residual macroblock;

when a first one of the plurality of intra prediction modes has been selected,

performing a first plurality of computations on the prediction macroblock to produce a DCT of the prediction macroblock;

when a second one of the plurality of intra prediction modes has been selected, performing a second plurality of computations on the prediction macroblock to produce the DCT of the prediction macroblock,

wherein the first plurality of computations and the second plurality of computations are different; and

adding the DCT of the prediction macroblock to the DCT of a residual macroblock to produce the DCT of the macroblock.

13. A method as in claim 12 , wherein performing the first plurality of computations on a prediction macroblock to produce the DCT of the prediction macroblock comprises:

performing a first number of additive operations; and

performing a second number of scaling operations; and

wherein performing the second plurality of computations on the prediction macroblock to produce the DCT of the prediction macroblock comprises:

performing a third number of additive operations; and

performing a fourth number of scaling operations.

14. A method as in claim 13 , wherein when the first one of the plurality of intra prediction modes is a DC mode, the first number of additive operations is zero and the second number of scaling operations is not greater than one.

15. A method as in claim 14 , wherein when the second one of the plurality of intra prediction modes is a vertical mode, the third number of additive operations is not greater than eight and the fourth number of scaling operations is not greater than six.

16. A method as in claim 14 , wherein when the second one of the plurality of intra prediction modes is a horizontal mode, the third number of additive operations is not greater than eight and the fourth number of scaling operations is not greater than six.

17. A method as in claim 14 , wherein when the second one of the plurality of intra prediction modes is a diagonal down left mode, the third number of additive operations is not greater than thirty-three and the fourth number of scaling operations is not greater than eleven.

18. A method as in claim 12 , further comprising: generating a video output by combining a reconstructed macroblock and the DCT of the macroblock.

19. A method as in claim 18 , wherein the video output is compressed and wherein the step of generating the video output comprises encoding the DCT of the macroblock.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
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To: NXP B.V.
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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To: FREESCALE SEMICONDUCTOR, INC.
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